Abstract: Spin-orbital quantum cellular automata logic devices and integrated circuits in the form of a substrate having a thin film of material on the substrate having strongly coupled spin-orbital states, the thin film being patterned to define at least one input and at least one output, and to perform at least one logic operation by associated arrangement of the spin-orbital states between the input and the output. The logic devices and integrated circuits further include an input device at each input to define the spin-orbital states at each input, and an output sensor at each output for sensing the spin-orbital states of the thin film at the output. In an integrated circuit, the output of one gate or circuit, in the form of the ferromagnetically aligned spins, can be directly coupled to the next gate or circuit, so that entire circuits can be fabricated and effectively interconnected, only requiring interfacing for overall.

Abstract: A method and apparatus for splitting/coupling optical signal(s). A unitary waveguide section having a first lateral dimension perpendicular to a propagation axis of the unitary section is provided. An offset waveguide section is optically coupled to the unitary waveguide section. The offset waveguide section has a second lateral dimension approximately equal to twice the first lateral dimension. Two branching waveguide sections having first ends are optically coupled to the offset section at the first ends.

Abstract: A heteostructure having a first and a second layer, in micrometer or smaller (e.g. nanometer) scale, arranged in a configuration defining at least one undercut at one side of the second layer, underneath the first layer, is described herein. In various embodiments, the undercut is filled with passivation materials to protect the layers underneath the first layer. Further, in various embodiments, a large metal contact layer including coverage of the first layer sidewall may be employed to provide significant increase in contact area, and to reduce the device contact resist value.

Abstract: An optical network, in the form of a 1×2N splitter, includes a series of interconnected distribution devices of varying size. Each distribution device may be an H-tree distribution device having an input waveguide and four output waveguides that provide in-phase, equal intensity copies of a signal received on the input waveguide. The network may include a primary H-tree distribution device and a plurality of secondary H-tree distribution devices each of a smaller size than the primary H-tree distribution device. Individual H-tree distribution devices may have a first stage Y-branch and a second stage Y-branch each of different radii of curvature. Further still, progressively smaller radius of curvature Y-branches may be used to form the 1×2N splitter, where N may be an even or odd integer.

Abstract: A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.

Abstract: An optical network is formed of multiple H-tree distribution devices, separated into different waveguide layers. The optical network receives an input optical signal, such as an optical clock signal, and makes duplicate copies of that input signal. The duplicate copies are routed through the connected H-tree distribution devices, which are arranged to produce identical, synchronized copies of the clock signal. The network can take the form of a 1×2N device, where 2N represents the number of these output signals. The H-tree distribution devices forming the network are of varying size and may be formed in different waveguide layers with different index of refraction differentials between the H-tree devices and surrounding claddings. In some forms, the optical network is integrated with optical-to-electrical converters, i.e., photodetectors, which take the optical output signals and convert them to synchronized electrical signals that may be communicated to digital circuits.

Abstract: A method and apparatus for splitting/coupling optical signal(s). A unitary waveguide section having a first lateral dimension perpendicular to a propagation axis of the unitary section is provided. An offset waveguide section is optically coupled to the unitary waveguide section. The offset waveguide section has a second lateral dimension approximately equal to twice the first lateral dimension. Two branching waveguide sections having first ends are optically coupled to the offset section at the first ends.

Abstract: Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids.

Abstract: Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids.

Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.

Abstract: Waveguide photodetector apparatus and methods employing an optical waveguide having a tapered section, which may be horizontally tapered, vertically tapered, or both. The apparatus also includes a photodetector with an intrinsic region, which in one embodiment may be tapered in a manner corresponding to a horizontal taper of the tapered section. The photodetector is arranged adjacent the tapered section such that the intrinsic region is coupled to the optical waveguide via an evanescent wave of a guided lightwave. The tapered section serves to force energy carried in the guided lightwave from the optical waveguide into the intrinsic region of the photodetector via the evanescent wave, thereby shortening the photodetector length.

Abstract: In accordance with embodiments of the methods of the present invention, a sacrificial layer provides an etch speed modification to effectively etch multiple semiconductor devices having dissimilar materials to a common layer or substrate with a common etch process. The time to etch remove a second exposed portion is compared with the time to etch remove a first exposed portion, and a sacrificial layer is deposited on the first exposed portion having a time to etch remove substantially equal to the difference. The sacrificial layer is provided to have predetermined material composition, material property and layer thickness, among other things, to provide a desired time to etch remove. The methods also provide for self-aligned via formation providing highly defined vias by the etch removal of sacrificial material rather than direct etching of the vie. The methods also provide planarization between two or more devices.

Abstract: Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Abstract: A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Abstract: An optical network, in the form of a 1×2N splitter, includes a series of interconnected distribution devices of varying size. Each distribution device is an H-tree distribution device having an input waveguide and four output waveguides that provide in-phase, equal intensity copies of a signal received on the input waveguide. The H-tree distribution devices may be formed from three interconnected Y-branches, each functioning as a 50/50 splitter, for example. The network includes H-tree distribution devices of different size. In an example form, a primary H-tree distribution device receives the input signal and routes it to a plurality of secondary H-tree distribution devices each of a smaller size than the primary H-tree distribution device.

Abstract: An optical network is formed of multiple H-tree distribution devices, separated into different waveguide layers. The optical network receives an input optical signal, such as an optical clock signal, and makes duplicate copies of that input signal. The duplicate copies are routed through the connected H-tree distribution devices, which are arranged to produce identical, synchronized copies of the clock signal. The network can take the form of a 1×2N device, where 2N represents the number of these output signals. The H-tree distribution devices forming the network are of varying size and may be formed in different waveguide layers with different index of refraction differentials between the H-tree devices and surrounding claddings. In some forms, the optical network is integrated with optical-to-electrical converters, i.e., photodetectors, which take the optical output signals and convert them to synchronized electrical signals that may be communicated to digital circuits.

Abstract: A method and apparatus to remove contamination and control electrostatic discharge in-situ in a semiconductor device manufacture process. In an embodiment, the method includes providing a reticle having first and second planar surfaces into a chamber. A circuit pattern of opaque material may be disposed on the first planar surface of the reticle. The method further includes irradiating the reticle using an ultraviolet light radiation beam to remove contamination disposed on the first and second planar surfaces of the reticle and to neutralize static electricity accumulated by the reticle.

Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.

Abstract: A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.

Abstract: A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.