Patents by Inventor Jun-Youn Kim

Jun-Youn Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180166302
    Abstract: In a method of forming a nitride semiconductor substrate, a nitride semiconductor substrate may be formed on a silicon substrate. A protection layer may be formed to cover a surface of the nitride semiconductor substrate. The silicon substrate may be removed by an etching process. The protection layer may limit and/or prevent the nitride semiconductor substrate from being etched during the etching process.
    Type: Application
    Filed: June 1, 2017
    Publication date: June 14, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sam-Mook KANG, Mi-Hyun KIM, Jun-Youn KIM, Young-Jo TAK
  • Publication number: 20180112330
    Abstract: In a method of manufacturing a GaN substrate, a capping layer may be formed on a first surface of a silicon substrate. A buffer layer may be formed on a second surface of the silicon substrate. The second surface may be opposite the first surface. A GaN substrate may be formed on the buffer layer by performing a hydride vapor phase epitaxy (HVPE) process. The capping layer and the silicon substrate may be removed.
    Type: Application
    Filed: March 29, 2017
    Publication date: April 26, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Mi-Hyun KIM, Sam-Mook KANG, Jun-Youn KIM, Young-Jo TAK, Young-Soo PARK
  • Patent number: 9947530
    Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Jo Tak, Sam Mook Kang, Mi Hyun Kim, Jun Youn Kim, Young Soo Park
  • Patent number: 9899565
    Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jo Tak, Sam Mook Kang, Mi Hyun Kim, Jun Youn Kim, Young Soo Park, Misaichi Takeuchi
  • Publication number: 20180030617
    Abstract: An apparatus includes a deposition chamber housing that accommodates a growth substrate, a supply nozzle to supply a deposition gas for forming a target large-size substrate on the growth substrate into the deposition chamber housing, a susceptor to support the growth substrate and expose a rear surface of the growth substrate to an etch gas, and an inner liner connected to the susceptor. The inner liner is to isolate the etch gas from the deposition gas and guide the etch gas toward the rear surface of the growth substrate. The susceptor includes a center hole that exposes the rear surface of the growth substrate and a support protrusion supporting the growth substrate, the support protrusion protruding toward the center of the center hole from an inner sidewall of the susceptor defining the center hole.
    Type: Application
    Filed: July 5, 2017
    Publication date: February 1, 2018
    Inventors: Sam-mook KANG, Jun-youn KIM, Young-jo TAK, Mi-hyun KIM, Young-soo PARK
  • Publication number: 20170358443
    Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.
    Type: Application
    Filed: January 6, 2017
    Publication date: December 14, 2017
    Inventors: Young Jo TAK, Sam Mook KANG, Mi Hyun KIM, Jun Youn KIM, Young Soo PARK
  • Patent number: 9793432
    Abstract: Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned distributed Bragg reflector (DBR) on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR and regions between patterns of the DBR.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Youn Kim, Bok-ki Min, Hyun-gi Hong, Jae-won Lee
  • Publication number: 20170286044
    Abstract: A multivision apparatus may include a display panel that includes a display screen including a first region and an adjacent second region. The first region may include first pixels, and the second region may include second pixels. The first pixels and the second pixels have different structures. The display panel may display a single image across the first region and the second region of the display screen. The multivision apparatus may include an array of interconnected display panels configured to collectively display an image, based on each given display panel displaying a separate sub-image in the first and second regions of the given display panel.
    Type: Application
    Filed: October 25, 2016
    Publication date: October 5, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun Youn KIM, Hyun Seong KUM, Young Hwan PARK
  • Patent number: 9666754
    Abstract: A method of manufacturing a semiconductor substrate may include: forming a buffer layer on a growth substrate; forming a plurality of openings in the buffer layer, the plurality of openings penetrating through the buffer layer and being spaced apart from one another; forming a plurality of cavities on the growth substrate, the plurality of cavities being aligned to respectively correspond to the plurality of openings; growing a semiconductor layer on the buffer layer, the growing the semiconductor layer including filling the plurality of openings with the semiconductor layer; and separating the buffer layer and the semiconductor layer from the growth substrate, wherein a diameter of each of the plurality of openings at a boundary between the growth substrate and the buffer layer is smaller than a diameter of each of the plurality of cavities at the boundary.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hwan Park, Sam Mook Kang, Jun Youn Kim, Mi Hyun Kim, Joo Sung Kim, Young Jo Tak
  • Publication number: 20170069785
    Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.
    Type: Application
    Filed: June 16, 2016
    Publication date: March 9, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young Jo TAK, Sam Mook KANG, Mi Hyun KIM, Jun Youn KIM, Young Soo PARK, Misaichi TAKEUCHI
  • Patent number: 9583340
    Abstract: Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7?k?13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Youn Kim, Jae-Kyun Kim, Joo-Sung Kim, Young-Soo Park, Young-Jo Tak
  • Patent number: 9525106
    Abstract: A semiconductor light emitting device includes: an n-type semiconductor layer and a p-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer; and an electron blocking layer disposed between the active layer and the p-type semiconductor layer and doped with a p-type dopant element. The electron blocking layer is formed of AlxGa1-xN, where 0<x?1. A plurality of first regions blocking overflow of electrons from the active layer to the p-type semiconductor layer and a plurality of second regions formed of InN are alternately disposed within the electron blocking layer.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Sun Maeng, Jun Youn Kim, Sung Min Choi, Kyung Ho Yoo
  • Publication number: 20160351748
    Abstract: A method of manufacturing a semiconductor substrate may include: forming a buffer layer on a growth substrate; forming a plurality of openings in the buffer layer, the plurality of openings penetrating through the buffer layer and being spaced apart from one another; forming a plurality of cavities on the growth substrate, the plurality of cavities being aligned to respectively correspond to the plurality of openings; growing a semiconductor layer on the buffer layer, the growing the semiconductor layer including filling the plurality of openings with the semiconductor layer; and separating the buffer layer and the semiconductor layer from the growth substrate, wherein a diameter of each of the plurality of openings at a boundary between the growth substrate and the buffer layer is smaller than a diameter of each of the plurality of cavities at the boundary.
    Type: Application
    Filed: April 15, 2016
    Publication date: December 1, 2016
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hwan PARK, Sam Mook KANG, Jun Youn KIM, Mi Hyun KIM, Joo Sung KIM, Young Jo TAK
  • Patent number: 9472624
    Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 18, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Joo-sung Kim, Moon-seung Yang
  • Patent number: 9449817
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Patent number: 9422638
    Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Jae-Kyun Kim, Su-hee Chae, Hyun-gi Hong
  • Patent number: 9337381
    Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Young-soo Park, Su-hee Chae
  • Publication number: 20160111592
    Abstract: Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned distributed Bragg reflector (DBR) on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR and regions between patterns of the DBR.
    Type: Application
    Filed: December 1, 2015
    Publication date: April 21, 2016
    Inventors: Jun-youn KIM, Bok-ki MIN, Hyun-gi HONG, Jae-won LEE
  • Publication number: 20160056325
    Abstract: A semiconductor light emitting device includes: an n-type semiconductor layer and a p-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer; and an electron blocking layer disposed between the active layer and the p-type semiconductor layer and doped with a p-type dopant element. The electron blocking layer is formed of AlxGa1-xN, where 0<x?1. A plurality of first regions blocking overflow of electrons from the active layer to the p-type semiconductor layer and a plurality of second regions formed of InN are alternately disposed within the electron blocking layer.
    Type: Application
    Filed: April 1, 2015
    Publication date: February 25, 2016
    Inventors: Jong Sun MAENG, Jun Youn KIM, Sung Min CHOI, Kyung Ho YOO
  • Patent number: 9257599
    Abstract: According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Young-soo Park, Young-jo Tak