Patents by Inventor Jun-Youn Kim

Jun-Youn Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8741706
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Publication number: 20140124818
    Abstract: A light emitting device (LED) includes a stress control layer having a compressive stress on a substrate, a bonding layer on the stress control layer, a semiconductor layer on the bonding layer and including an active region for emitting light on the bonding layer, a first electrode on a lower surface of the substrate, and a second electrode on the semiconductor layer. The compressive stress of the stress control layer is between about 1 and about 20 GPa.
    Type: Application
    Filed: April 4, 2013
    Publication date: May 8, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-sik HWANG, Jun-youn KIM, Su-hee CHAE
  • Patent number: 8716749
    Abstract: Substrate structures and methods of manufacturing the substrate structures. A substrate structure is manufactured by forming a protrusion area of a substrate under a buffer layer, and forming a semiconductor layer on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Hyun-gi Hong, Young-jo Tak, Jae-won Lee, Hyung-su Jeong
  • Publication number: 20140113437
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Application
    Filed: January 2, 2014
    Publication date: April 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Su-hee CHAE, Hyun-gi HONG, Young-jo TAK
  • Patent number: 8703512
    Abstract: A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-won Lee, Bok-ki Min, Jun-youn Kim, Young-jo Tak, Hyung-su Jeong
  • Publication number: 20140061663
    Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 6, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jun-youn KIM, Joo-sung KIM, Moon-seung YANG
  • Publication number: 20140057381
    Abstract: Example embodiments are directed to a light-emitting device including a patterned emitting unit and a method of manufacturing the light-emitting device. The light-emitting device includes a first electrode on a top of a semiconductor layer, and a second electrode on a bottom of the semiconductor layer, wherein the semiconductor layer is a pattern array formed of a plurality of stacks. A space between the plurality of stacks is filled with an insulating layer, and the first electrode is on the insulating layer.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 27, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyung-su JEONG, Young-soo PARK, Su-hee CHAE, Bok-ki MIN, Jun-youn KIM, Hyun-gi HONG, Young-jo TAK, Jae-won LEE
  • Publication number: 20140042492
    Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Publication number: 20140042391
    Abstract: A semiconductor device includes a first coalescent layer, a second coalescent layer, a nitride stacked structure on the second coalescent layer, and a third layer between the first and second coalescent layers. The first coalescent layer includes a plurality of formations that are partially merged, and the third layer is disposed on the formations to allow a first type of stress to be generated in an area which includes the first coalescent layer and a second type of stress to be generated in an area which includes the second coalescent layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 13, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Joo-sung KIM, Young-jo TAK
  • Publication number: 20140045284
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Patent number: 8643059
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Publication number: 20140014990
    Abstract: Lights-emitting device (LED) packages, and methods of manufacturing the same, include at least one light-emitting structure. The at least one light-emitting structure includes a first compound semiconductor layer, an active layer, and a second compound semiconductor layer that are sequentially stacked, at least one first metal layer connected to the first compound semiconductor layer, a second metal layer connected to the second compound semiconductor layer, a substrate having a conductive bonding layer on a first surface of the substrate, and a bonding metal layer configured for eutectic bonding between the at least one first metal layer and the conductive bonding layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Jae-kyun KIM, Joo-sung KIM, Moon-seung YANG, Su-hee CHAE, Young-jo TAK, Hyun-gi HONG
  • Publication number: 20140001438
    Abstract: A semiconductor device includes a buffer structure on a silicon substrate, and at least one gallium nitride-based semiconductor layer on the buffer structure. The buffer structure includes a plurality of nitride semiconductor layers and a plurality of stress control layers that are alternately disposed with the plurality of nitride semiconductor layer. The plurality of stress control layers include a IV-IV group semiconductor material.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 2, 2014
    Inventors: Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI, Young-jo TAK
  • Publication number: 20130334496
    Abstract: A semiconductor device includes a silicon substrate; a nitride nucleation layer disposed on the silicon substrate; at least one superlattice layer disposed on the nitride nucleation layer; and at least one gallium nitride-based semiconductor layer disposed on the superlattice layer. The at least one superlattice layer includes a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 19, 2013
    Inventors: Jae-kyun KIM, Jun-youn KIM, Young-jo TAK
  • Publication number: 20130328054
    Abstract: A gallium nitride based semiconductor device includes a silicon-based layer doped simultaneously with boron (B) and germanium (Ge) at a relatively high concentration, a buffer layer on the silicon-based layer, and a nitride stack on the buffer layer. A doping concentration of boron (B) and germanium (Ge) may be higher than 1×1019/cm3.
    Type: Application
    Filed: December 13, 2012
    Publication date: December 12, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo TAK, Jae-kyun KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Patent number: 8592839
    Abstract: Example embodiments are directed to a light-emitting device including a patterned emitting unit and a method of manufacturing the light-emitting device. The light-emitting device includes a first electrode on a top of a semiconductor layer, and a second electrode on a bottom of the semiconductor layer, wherein the semiconductor layer is a pattern array formed of a plurality of stacks. A space between the plurality of stacks is filled with an insulating layer, and the first electrode is on the insulating layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-su Jeong, Young-soo Park, Su-hee Chae, Bok-ki Min, Jun-youn Kim, Hyun-gi Hong, Young-jo Tak, Jae-won Lee
  • Publication number: 20130309794
    Abstract: A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 21, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-won LEE, Bok-Ki MIN, Jun-youn KIM, Young-jo TAK, Hyung-su JEONG
  • Publication number: 20130302953
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.
    Type: Application
    Filed: July 17, 2013
    Publication date: November 14, 2013
    Inventors: Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Patent number: 8581276
    Abstract: Example embodiments relate to a light emitting device and a method of fabricating the light emitting device. The light emitting device may include an n-type clad layer including a plurality of nitride semiconductor layers, at least one interlayer disposed between the plurality of nitride semiconductor layers, a via hole in which a first electrode is formed, a p-type clad layer, and an active layer between the n-type clad layer and the p-type clad layer.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-won Lee, Su-hee Chae, Jun-youn Kim, Young-jo Tak
  • Patent number: 8564009
    Abstract: According to an example embodiment, a vertical light emitting device (LED) includes a semiconductor layer including an active layer configured to emitting light, a first electrode on a first side of the semiconductor layer, and a second electrode on a second side of the semiconductor layer opposite to the first electrode. At least one of the first and second electrodes includes a metal electrode pattern and a transparent electrode pattern. The transparent electrode pattern is in a region between segment electrodes of the metal electrode pattern. The transparent electrode pattern is electrically connected to the metal electrode pattern.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bok-ki Min, Young-soo Park, Su-hee Chae, Jun-youn Kim, Hyun-gi Hong, Young-jo Tak