Abstract: Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned dispersion Bragg reflection (DBR) layer on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR layer and regions between patterns of the DBR layer.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.

Abstract: A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location.

Abstract: Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned dispersion Bragg reflection (DBR) layer on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR layer and regions between patterns of the DBR layer.

Abstract: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.

Abstract: A jig for use in etching supports an etching target while an etching process is performed and surrounds a remaining region of the etching target except for a portion of the etching target, so as to expose the portion of the etching target. Accordingly, a stable support of the etching target during the etching process may be provided, and thus an etching of an undesired region may be prevented, and a stable production yield may be accomplished.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.

Abstract: According to an example embodiment, a power device includes a substrate, a nitride-containing stack on the substrate, and an electric field dispersion unit. Source, drain, and gate electrodes are on the nitride-containing stack. The nitride-containing stack includes a first region that is configured to generate a larger electric field than that of a second region of the nitride-containing stack. The electric field dispersion unit may be between the substrate and the first region of the nitride-containing stack.

Abstract: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

Abstract: According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer.

Abstract: Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer formed of a metal between a semiconductor layer and a bonding substrate. When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented.

Abstract: According to an example embodiment, a vertical light emitting device (LED) includes a semiconductor layer including an active layer configured to emitting light, a first electrode on a first side of the semiconductor layer, and a second electrode on a second side of the semiconductor layer opposite to the first electrode. At least one of the first and second electrodes includes a metal electrode pattern and a transparent electrode pattern. The transparent electrode pattern is in a region between segment electrodes of the metal electrode pattern. The transparent electrode pattern is electrically connected to the metal electrode pattern.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

Abstract: A gallium nitride (GaN) light emitting device and a method of manufacturing the same are provided, the method including sequentially forming a buffer layer and a first nitride layer on a silicon substrate, and forming a plurality of patterns by dry etching the first nitride layer. Each pattern includes a pair of sidewalls facing each other. A reflective layer is deposited on the first nitride layer so that one sidewall of the pair is exposed by the reflective layer. An n-type nitride layer that covers the first nitride layer is formed by horizontally growing an n-type nitride from the exposed sidewall, and a GaN-based light emitting structure layer is formed on the n-type nitride layer.

Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.

Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.

Abstract: Example embodiments of the present invention relate to a light emitting device having a connection structure and a method of manufacturing the light emitting device. The method of manufacturing may include forming a light emitting region and electrode layers on a substrate in which a plurality of cell regions and a bridge for partially connecting the cell regions are disposed, thereby providing a light emitting device that controls stress with relative ease and integrates electrical connections between the cell regions.