Patents by Inventor Jun Yuan

Jun Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190105694
    Abstract: In view of the problem of uneven performance of railhead sections of pearlitic rail manufactured with existing technique and the poor performance of the pearlitic rail obtained, the invention provides a manufacturing method for high-carbon and high-strength and toughness pearlitic rail, including the following steps to: a. hot roll the steel billet into rail, with a final rolling temperature of 900-1000° C.; b. blow a cooling medium to the top surface of railhead, wherein, the two sides of railhead and the lower jaws on two sides of railhead when the center of top surface of rail is air-cooled to 800-850° C.; then air-cool the rail to room temperature after the center of top surface of rail is cooled to 480-530° C. By controlling the composition of steel and adopting a two-stage accelerated cooling, a high-carbon rail is produced with better strength and excellent toughness which is suitable for heavy-haul railway.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 11, 2019
    Inventors: Zhenyu HAN, Ming ZOU, Hua GUO, Jun YUAN
  • Publication number: 20190105693
    Abstract: Provided is a manufacturing method for high-toughness and plasticity hypereutectoid rail, including: a. hot rolling the steel billet into rail; b. blowing a cooling medium to the top surface of railhead, wherein, the two sides of railhead and the lower jaws on the two sides of railhead after the center of top surface of rail is air-cooled to 800-850° C., and cooling the rail until the center temperature of the top surface is 520-550° C.; c. stop blowing the cooling medium to the lower jaws on the two sides of railhead, continue blowing the cooling medium to the top surface of railhead and the two sides of railhead, and air cool the rail to room temperature after the surface temperature of railhead is cooled to 430-480° C. The resulting hypereutectoid rail has higher toughness and plasticity than existing products, which is suitable for heavy-haul railway, especially for small radius curve sections.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 11, 2019
    Inventors: Zhenyu HAN, Ming ZOU, Hua GUO, Jun YUAN
  • Publication number: 20190106761
    Abstract: In view of the low comprehensive strength and toughness of pearlitic rail manufactured by existing techniques, the invention provides a manufacturing method for rail of railway with passenger and freight mixed traffic, including the following steps: a. hot roll steel billet into rail, with a final rolling temperature of 900-1000° C.; b. blow a cooling medium to the top surface of railhead, the two sides of railhead and the lower jaws on two sides of railhead when the center of top surface of rail is air-cooled to 800-850° C.; and then air-cool the rail to the room temperature after the center of top surface of rail is cooled to 520-550° C. By controlling the composition of steel and adopting a two-stage accelerated cooling, the invention is able to produce a rail with better performance which is suitable for railway with passenger and freight mixed traffic.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 11, 2019
    Inventors: Zhenyu HAN, Ming ZOU, Hua GUO, Jun YUAN
  • Patent number: 10247617
    Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: April 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lixin Ge, Periannan Chidambaram, Bin Yang, Jiefeng Jeff Lin, Giridhar Nallapati, Bo Yu, Jie Deng, Jun Yuan, Stanley Seungchul Song
  • Patent number: 10214799
    Abstract: The present invention relates to a heat treatment method for increasing the depth of hardening layer in a steel rail, and belongs to the field of steel rail production process. The technical problem to be solved in the present invention is to provide a heat treatment method for increasing the depth of hardening layer in a steel rail and a steel rail obtained with the method. The method comprises the following steps: cooling a finished rolling steel rail by natural cooling, till the temperature at the center of rail head surface is 660˜730° C.; cooling the steel rail by accelerated cooling at 1.5˜3.5° C./s cooling rate, till the temperature at the center of rail head surface is 500˜550° C.; increasing the cooling rate by 1.0˜2.0° C./s and further cooling down the steel rail, till the temperature at the center of rail head surface is 450° C. or lower; then, stopping the accelerated cooling, and cooling down the steel rail by air cooling to room temperature.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 26, 2019
    Assignees: PanGang Group Panzhihua Iron & Steel Research Institute Co., Ltd., Pangang Group Panzhihua Steel & Vanadium Co., Ltd.
    Inventors: Zhenyu Han, Ming Zou, Jihai Jia, Hua Guo, Dadong Li, Yong Deng, Chunjian Wang, Jun Yuan, Chongmu Chen
  • Patent number: 10219244
    Abstract: A device may obtain information. The information may represent a distance between a first user device and a second user device. The first user device and the second user device may share a destination address. The device may receive a first message associated with a call. The first message may be received based on the call having been made to the destination address. The device may determine, based on the information, whether to provide a second message associated with the call or a notification associated with the call. The device may selectively provide the second message or the notification based on determining whether to provide the second message or the notification.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: February 26, 2019
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Jun Yuan, Yuk Lun Li
  • Patent number: 10205560
    Abstract: Methods described herein are for wireless communication systems. One aspect of the invention is directed to a method for a HARQ process, in which the HARQ process includes a first transmission of an encoder packet and at least one retransmission. The method involves allocating a transmission resource for each respective transmission. The method involves transmitting control information from a base station to a mobile station for each respective transmission. The control information includes information to uniquely identify the HARQ process and an identification of one of a time resource, a frequency resource and a time and frequency resource that is allocated for the transmission. In some embodiments of the invention, specific control information is signalled from a base station to a mobile station to enable RAS-HARQ operation. In some embodiments of the invention, retransmission signaling in included as part of regular unicast signaling used for both first transmission and retransmissions.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 12, 2019
    Assignee: Apple Inc.
    Inventors: Mo-han Fong, Sophie Vrzic, Robert Novak, Jun Yuan, Dong-Sheng Yu
  • Patent number: 10196781
    Abstract: The present invention discloses a method for preparing hypereutectoid steel rail in which the composition of the billets adopted is: C: 0.86-1.05 wt. %; Si: 0.3-1 wt. %; Mn: 0.5-1.3 wt. %; Cr: 0.15-0.35 wt. %; Cu: 0.3-0.5 wt. %; P: 0.02-0.04 wt. %; S: ?0.02 wt. %; Ni: ½-? of the content of Cu; at least one of V, Nb and Re; Fe and unavoidable impurities of the rest. The present invention further provides a hypereutectoid steel rail prepared by the foregoing method. By the hypereutectoid steel rail preparation method provided by the present invention, the high-carbon billets with a specific composition provided by the present invention can be made into hypereutectoid steel rails with good corrosion resistance and tensile properties.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 5, 2019
    Assignees: PANGANG GROUP PANZHIHUA IRON & STEEL RESEARCH INSTITUTE CO., LTD., PANGANG GROUP PANZHIHUA STEEL & VANADIUM CO., LTD.
    Inventors: Zhenyu Han, Ming Zou, Hua Guo, Yuan Wang, Dadong Li, Yong Deng, Jun Yuan
  • Patent number: 10181403
    Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Da Yang, Yanxiang Liu, Jun Yuan, Kern Rim
  • Patent number: 10141305
    Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Haining Yang, Jun Yuan, Kern Rim, Periannan Chidambaram
  • Patent number: 10134734
    Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jun Yuan, Yanxiang Liu, Kern Rim
  • Publication number: 20180326079
    Abstract: The invention provides a conjugate comprising a biomolecule linked to a fatty acid via a linker wherein the fatty acid has the following Formulae A1, A2 or A3: wherein R1, R2, R3, R4, Ak, n, m and p are defined herein. The invention also relates to a method for manufacturing the conjugate of the invention such as GDF15 conjugate, and its therapeutic uses such as treatment or prevention of metabolic disorders or diseases, type 2 diabetes mellitus, obesity, pancreatitis, dyslipidemia, alcoholic and nonalcoholic fatty liver disease/steatohepatitis and other progressive liver diseases, insulin resistance, hyperinsulinemia, glucose intolerance, hyperglycemia, metabolic syndrome, hypertension, cardiovascular disease, atherosclerosis, peripheral arterial disease, stroke, heart failure, coronary heart disease, diabetic complications (including but not limited to chronic kidney disease), neuropathy, gastroparesis and other metabolic disorders.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 15, 2018
    Inventors: David Weninger BARNES, Avirup BOSE, Alexandra Marshall BRUCE, Alokesh DUTTAROY, Chikwendu IBEBUNJO, Aaron KANTER, Louise Clare KIRMAN, Changgang LOU, Aimee Richardson USERA, Ken YAMADA, Jun YUAN, Frederic ZECRI
  • Patent number: 10113096
    Abstract: The present invention provides a resin composition including aluminum oxide (A) containing molybdenum having a size on the order of ?m or less and a resin (B); and a resin molded body formed by molding the resin composition. Also, the present invention provides a heat-dissipating material containing the resin composition; and a heat-dissipating member containing the resin molded body. The heat-dissipating member of the present invention can be used for electronic parts such as electronic devices, electric devices, OA devices or for LED illumination.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: October 30, 2018
    Assignee: DIC Corporation
    Inventors: Jian-Jun Yuan, Hiroshi Kinoshita
  • Patent number: 10107869
    Abstract: The present invention provides a detection circuit, which comprises a first detection path and a second detection path for detecting the state of a power source under test. A first current is generated on the first detection path according to power source under test; a second current is generated on the second detection path according to the power source under test. The detection circuit generates a detection signal according to the first current and the second current. The detection signal represents the state of the power source under test.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: October 23, 2018
    Assignee: Q-Silicon Technologies Corp.
    Inventors: Jun-Yuan Chen, Chih-Te Hung, Cheng-Chung Yeh
  • Publication number: 20180293820
    Abstract: A method includes obtaining data associated with operation of an aircraft and determining a first operational phase of the aircraft based on the data. The method includes identifying a candidate operational phase transition from the first operational phase to a candidate operational phase based on a first portion of the data satisfying a first condition associated with the candidate operational phase, the first portion of the data corresponding to a first time. The method includes evaluating a second portion of the data based on a second condition associated with the candidate operational phase, the second portion of the data corresponding to a second time that is subsequent to the first time. The method further includes, based on the second condition being satisfied, generating an operational phase transition indication that indicates an occurrence of an operational phase transition to the candidate operational phase at the first time.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Inventors: Changzhou Wang, Jun Yuan, Brian K. Predmore
  • Publication number: 20180294925
    Abstract: Methods described herein are for wireless communication systems. One aspect of the invention is directed to a method for a HARQ process, in which the HARQ process includes a first transmission of an encoder packet and at least one retransmission. The method involves allocating a transmission resource for each respective transmission. The method involves transmitting control information from a base station to a mobile station for each respective transmission. The control information includes information to uniquely identify the HARQ process and an identification of one of a time resource, a frequency resource and a time and frequency resource that is allocated for the transmission. In some embodiments of the invention, specific control information is signalled from a base station to a mobile station to enable RAS-HARQ operation. In some embodiments of the invention, retransmission signaling in included as part of regular unicast signaling used for both first transmission and retransmissions.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Mo-han Fong, Sophie Vrzic, Robert Novak, Jun Yuan, Dong-Sheng Yu
  • Patent number: 10090305
    Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jun Yuan, Yanxiang Liu, Kern Rim
  • Patent number: 10065119
    Abstract: A method including generating, by a terminal, a creation request containing game information, sending, by the terminal, the creation request to a game server, receiving, by the terminal, a graphic information code generated by a management server according to the game information, and displaying the graphic information code on the terminal.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 4, 2018
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Min Yan, Yiping Guo, Jianghao Zhu, Siquan Chen, Jun Zhang, Yong Fan, Jun Yuan, Xin Zhang
  • Publication number: 20180248920
    Abstract: A user device registers with a proxy-call session control function device (P-CSCF) associated with an Internet protocol (IP) multimedia subsystem (IMS). The user device forwards a request to the P-CSCF requesting a session via the IMS for an IMS call. If a response to the request is not received from the P-CSCF during a time period after forwarding the request, the user device attempts to newly register with the P-CSCF. If the new registration is successful, the user device re-forwards the request to the P-CSCF. Otherwise, if the new registration with the P-CSCF is unsuccessful, the user device registers with a different P-CSCF and forwards the request to the second P-CSCF.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Muhammad Salman Nomani, Andrew E. Youtz, Jun Yuan
  • Publication number: 20180197743
    Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.
    Type: Application
    Filed: March 2, 2018
    Publication date: July 12, 2018
    Inventors: Da YANG, Yanxiang LIU, Jun YUAN, Kern RIM