Abstract: The present general inventive concept includes a wave soldering apparatus, a soldering method using the wave soldering apparatus, and a method of forming a solder bump for a flip chip. The wave soldering apparatus includes a solder bath containing a molten solder. A nozzle is arranged in the solder bath so as to upwardly spout the molten solder toward a bottom surface of a substrate that passes an upper portion of the solder bath. A liquid that is separated from the molten solder is contained in a downstream area of the solder bath, and buoyancy is applied to the molten solder, which is adhered to the substrate, by the liquid. Since the amount of the molten solder adhered to the substrate is increased by the buoyancy, it is possible to form the solder bump to have a height sufficient to use it as a flip chip.

Abstract: A projection type image display apparatus includes: a cabinet; a screen which is provided in the cabinet; a display device which is placed inside the cabinet and forms an image; and an optical system which projects an image formed by the display device to the screen and comprises at least one mirror, a supporter for supporting the mirror, and a frame through which the supporter is fastened to the cabinet, all of the mirror, the supporter and the frame being disposed within a single interior space formed by the cabinet and the screen.

Abstract: A voltage-controlled oscillator (VCO) circuit includes a level shifter, and a semiconductor device includes the VCO circuit. The VCO circuit includes an input voltage receiver, a current mirror, and a frequency oscillator. The input voltage receiver receives a first voltage input to the VCO circuit so as to generate a first current. The current mirror copies the first current so as to generate a second current. The frequency oscillator oscillates in response to the second current. The input voltage receiver includes a level shifter and a first current generator. The level shifter shifts a voltage level of the first voltage to a voltage level of a second voltage. The first current generator generates the first current corresponding to the second voltage.

Abstract: The present invention relates to a method and system for the management of the mobility, the management of an idle mode, the registration management (management of attachment and detachment), and the location management (management of tracking area) of a terminal by using a non-access stratum (i.e., network stratum, hereinafter referred to as “NAS”) in a mobile telecommunication network. To this end, the method for the management of mobility, the management of an idle mode, the registration management, and the location management of a terminal by using a NAS protocol, i.e., messages, according to an embodiment of the present invention, includes a terminal (hereinafter, referred to as “UE”) and a mobility management entity (hereinafter, referred to as “MME”), and addresses to a method for efficiently processing security protected NAS messages if received messages are security protected NAS messages, in a case of sending or receiving messages serving as EMM (EPS Mobility Management) messages, i.e.

Abstract: A super-resolution optical recording medium includes a reflective layer formed on a substrate, a recording layer for recording information thereon, a super-resolution layer made of a chalcogenide semiconductor material, and a first and a second dielectric layers laminated on upper and lower surfaces of the super-resolution layer. The recording layer is made of a material that has a decomposition temperature higher than an information reproduction temperature and does not form bubble recording marks during recording, and the super-resolution layer contains one or more elements selected from the group consisting of nitrogen, oxygen, carbon, and boron.

Abstract: In a multilayer structure and a method of forming the same, a conductive layer including a metal nitride and a dielectric layer positioned on a surface of the conductive layer and having a high dielectric constant. The metal nitride comprises one of niobium, vanadium and compositions thereof. Thus, the EOT and leakage current of the multilayer structure may be sufficiently improved.

Abstract: Disclosed are a hinge unit which couples a first member and a second member, the hinge unit including: a conic shaft which is coupled to the first member, and comprises a hinge pivot, a conic unit of a truncated cone shape, the radius of which is extended in an end area of the hinge pivot, and a first rocking unit formed to an outer surface of the conic unit; and a conic sleeve which is coupled to the second member, and comprises a sleeve main body formed with a conic accommodating unit having a shape corresponding to the conic unit in an inner part of the conic accommodating unit, and a second rocking unit formed to an inner surface of the conic accommodating unit to be coupled with the first rocking unit.

Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract: A vacuum type pickup apparatus may include an absorption pad having an absorption inlet for contacting and/or picking up an object. A pad holder may be connected to the absorption pad. The pad holder may also have a vacuum line. A separator may be provided in the pad holder for forcibly releasing the object from the absorption inlet of the absorption pad. During the forcible release of the object, the air around the absorption pad may be drawn into the pad holder, thus reducing or preventing the potential contamination by impurities of the object as well as the equipment around the object. Also, an additional vacuum extinguisher may not be required, thus simplifying the structure of the vacuum type pickup apparatus and reducing installation costs. Furthermore, the object may be picked up and released in a relatively expedient, safe, and accurate manner, despite the suction force of the vacuum that may be maintained in the pad holder.

Abstract: In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.

Abstract: A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode.

Abstract: A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.

Abstract: The present invention relates to a backlight assembly and a liquid crystal display (“LCD”) having the same. The backlight assembly includes a light source unit including a printed circuit board (“PCB”) and a plurality of light emitting diodes (“LEDs”) mounted on a side of the PCB, a receiving member including a base plate and a plurality of walls that extend from the base plate at an angle and receive the light source unit, and a plurality of through holes or uneven patterns formed in a region of the receiving member where at least the light source unit is disposed.

Abstract: A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire.

Abstract: A projection-type display apparatus and a display method thereof are disclosed, the projection-type display apparatus including a coated portion which is formed on a surface of a substrate, and which scans a video onto a screen, and a patterned portion which is formed on another surface of the substrate in a serrated pattern, wherein the serrated pattern is formed on the substrate according to the surface area of the patterned portion and the depth of the serrated pattern. A serrated pattern is formed on a substrate forming a reflective portion to reflect a video on a screen, so the cooling surface area of the substrate is increased, thereby compensating for distortions in video scanned onto the screen.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.

Abstract: Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

Abstract: A casing to support a solid state device SSD therein and super capacitors therein to be electronically connected together.