Patents by Inventor Jung Yu

Jung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240053247
    Abstract: The present invention provides a practical protection performance test evaluation technology of CBRN protective clothing according to mass transfer characteristics of an aerosol, which is to break away from the existing static CBRN protection test cell and reflect an air flow around the CBRN protection and body motions of individual soldiers, and dynamically design a Swatch test cell in a geometric shape that can be installed inside a wind tunnel, and reflect an aerosol flow that can more closely simulate battlefield environment.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 15, 2024
    Inventors: Seung Jung YU, Hyun Sook JUNG, Hee Soo JUNG, Goon Hyeok KIM, Jae Heon LEE
  • Patent number: 11901267
    Abstract: The present application provides a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region, and including a first recess extending into the semiconductor substrate and disposed in the array region; an isolation structure surrounded by the semiconductor substrate and disposed in the peripheral region; and a word line disposed within the first recess, wherein the word line includes an insulating layer conformal to the first recess and a conductive member surrounded by the insulating layer, and the conductive member includes a second recess extending into the conductive member and toward the semiconductor substrate. A method of manufacturing the memory device is also disclosed.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jung-Yu Wu
  • Publication number: 20230404993
    Abstract: Disclosed herein is a method for alleviating a chronic liver disease, comprising administrating to a subject in need thereof a pharmaceutical composition containing rosoxacin.
    Type: Application
    Filed: November 11, 2022
    Publication date: December 21, 2023
    Inventors: Jinn-Moon Yang, Shey-Cherng Tzou, Ming-Lung Yu, Yun-Ti Chen, Hsiao-Chen Huang, Jung-Yu Lee
  • Publication number: 20230389333
    Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Hui-Hsien WEI, Yen-Chung HO, Chia-Jung YU, Yong-Jie WU, Pin-Cheng HSU
  • Patent number: 11830280
    Abstract: An image processing circuit for controlling a panel is configured to: receive information of a fixed pattern noise (FPN) corresponding to a first sensing zone of the panel, wherein the first sensing zone is determined according to a touch position of a finger; scan the first sensing zone to perform fingerprint sensing on the finger, to receive a plurality of raw sensing signals; remove the FPN from the plurality of raw sensing signals to generate a plurality of modified sensing signals; and output a plurality of fingerprint data to a host for fingerprint recognition, wherein the plurality of fingerprint data are converted from the plurality of modified sensing signals.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 28, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jung-Chen Chung, Chi-Ting Chen, Jung-Yu Tsai
  • Publication number: 20230380186
    Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Mauricio MANFRINI, Chung-Te LIN
  • Patent number: 11825661
    Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hui-Hsien Wei, Yen-Chung Ho, Chia-Jung Yu, Yong-Jie Wu, Pin-Cheng Hsu
  • Publication number: 20230371278
    Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Mauricio MANFRINI, Chung-Te LIN
  • Publication number: 20230361221
    Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Inventors: Yong-Jie Wu, Hui-Hsien Wei, Yen-Chung Ho, Mauricio Manfrini, Chia-Jung Yu, Chung-Te Lin, Pin-Cheng Hsu
  • Publication number: 20230348003
    Abstract: A device for adjusting a seat height includes a fixation seat, an outer tube, an inner tube received in the outer tube, a cylinder housed in the inner tube, and a piston rod accommodated in the cylinder and combined with the inner tube. The fixation seat is attached to a bicycle seat. The outer tube is adapted to be connected with a bicycle frame. The piston rod can be displaced relative to the cylinder, so that the inner tube is driven by the piston rod to move relative to the outer tube within a displacement stroke, so as to adjust the height of the bicycle seat. In addition, the inner tube can be displaced relative to the piston rod by the rotation of the piston rod, so that the rider can adjust the bicycle seat height according to his own height or specific needs.
    Type: Application
    Filed: November 4, 2022
    Publication date: November 2, 2023
    Inventor: Jung-Yu Hsu
  • Publication number: 20230354191
    Abstract: A method and an apparatus for allocating a flexible transmission slot in a wireless local area network (LAN) system are disclosed. A flexible transmission slot allocation method of an access point (AP) in a wireless local area network (WLAN) system according to an exemplary embodiment includes transmitting a beacon including a traffic indication map (TIM) bit to a station, receiving a power save poll (PS-Poll) from the station in a slot implicitly allocated by the TIM bit, and transmitting an acknowledgement (ACK) including transmission slot allocation information on downlink data to the station.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 2, 2023
    Inventors: Jae Seung LEE, Mln Ho CHEONG, Hyoung Jin KWON, Hee Jung YU, Jae Woo PARK, Sok Kyu LEE
  • Publication number: 20230345740
    Abstract: A memory device and method of making the same, the memory device including bit lines disposed on a substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Inventors: Yen-Chung HO, Hui-Hsien Wei, Mauricio MANFRINI, Chia-Jung Yu, Yong-Jie Wu, Ken-Ichi Goto, Pin-Cheng Hsu
  • Publication number: 20230340243
    Abstract: The present invention relates to a thermoplastic resin composition including a polyolefin-polystyrene-based multiblock copolymer having a structure in which a polystyrene chain is attached to both ends of a polypropylene and polyolefin chain, and the thermoplastic resin composition according to the present invention has excellent elongation and tensile strength as well as high fluidity properties, and thus, may exhibit excellent molding processability.
    Type: Application
    Filed: July 30, 2021
    Publication date: October 26, 2023
    Applicant: LG Chem, Ltd.
    Inventors: Hyun Mo Lee, Seul Ki Im, Ji Hyun Park, Yun Kon Kim, Seung Jung Yu, Seok Pil Sa, Ki Soo Lee, Eun Ji Shin
  • Publication number: 20230339068
    Abstract: A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves. The method further includes spreading the slurry across a second region, surrounding the first region of the polishing pad at a second rate different from the first rate, wherein the second region includes a plurality of second grooves. The method further includes spreading the slurry across a third region, surrounding the second region of the polishing pad at a third rate less than the first rate and the second rate, wherein the third region includes a plurality of third grooves.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 26, 2023
    Inventors: ChunHung CHEN, Jung-Yu LI, Sheng-Chen WANG, Shih-Sian HUANG
  • Publication number: 20230326969
    Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 12, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Jeng Hwa Liao, Zong-Jie Ko, Hsing-Ju Lin, Jung-Yu Shieh, Ling-Wuu Yang
  • Publication number: 20230303753
    Abstract: The present invention relates to a method for preparing a polyolefin-polystyrene-based multiblock copolymer having a uniform structure and showing excellent physical properties through continuous type coordination polymerization and batch type anionic polymerization.
    Type: Application
    Filed: August 25, 2021
    Publication date: September 28, 2023
    Applicant: LG Chem, Ltd.
    Inventors: Yun Kon Kim, Seul Ki Im, Hyun Mo Lee, Ji Hyun Park, Dong Min Kim, Mi Kyung Kim, Ki Soo Lee, Eun Ji Shin, Seok Pil Sa, Seung Jung Yu
  • Patent number: 11767634
    Abstract: A sprayable and hygroscopic ink for a digital printing process on a fabric includes 3.0 parts by weight to 6.0 parts by weight of a colorant, 0.5 parts by weight to 2.0 parts by weight of a hygroscopic agent, 0.5 parts by weight to 1.0 part by weight of a surfactant, and a balance of a solvent, in which a pH value of the hygroscopic agent is between 6.0 and 8.5 at 25° C., and a particle diameter D90 of the sprayable and hygroscopic ink is between 180 nm and 220 nm.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 26, 2023
    Assignee: TAIWAN TEXTILE RESEARCH INSTITUTE
    Inventors: Jung-Yu Tsai, Chia-Yi Lin
  • Patent number: 11762507
    Abstract: A fingerprint sensing device that includes an analog-front-end (AFE) circuit, an analog-to-digital converter (ADC) and a correction circuit is introduced. The AFE circuit generates an image signal, and the ADC converts the image signal to an output digital code. The correction circuit receives a plurality of first output digital codes that are generated by performing a plurality of first fingerprint sensing operations in a plurality of first exposure time periods. The correction circuit is further configured to calculate a second exposure time period for a second fingerprint sensing operation according to the first output digital codes and the first exposure time periods, wherein the fingerprint sensing device performs the second fingerprint operation in the second exposure time period to generate a second output digital code.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: September 19, 2023
    Assignee: Novatek Microelectronics Corp.
    Inventors: Min Huang, Jung-Yu Tsai, Chi-Ting Chen
  • Publication number: 20230287208
    Abstract: The present invention relates to a thermoplastic resin composition including a polyolefin-polystyrene-based multi-block copolymer having a structure in which a polystyrene chain is attached to both ends of a polypropylene and polyolefin chain, and the thermoplastic resin composition according to the present invention exhibits high fluidity properties as well as soft feel and high restoring force.
    Type: Application
    Filed: August 6, 2021
    Publication date: September 14, 2023
    Applicant: LG Chem, Ltd.
    Inventors: Tae Hee Kim, Ki Soo Lee, Eun Ji Shin, Seok Pil Sa, Seul Ki Im, Hyun Mo Lee, Ji Hyun Park, Yun Kon Kim, Seung Jung Yu
  • Patent number: D1016283
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 27, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu