Abstract: The present invention relates to a thermoplastic resin composition including a polyolefin-polystyrene-based multi-block copolymer having a structure in which a polystyrene chain is attached to both ends of a polypropylene and polyolefin chain, and the thermoplastic resin composition according to the present invention has significantly improved low-temperature and room temperature impact strength properties as well as high fluidity properties, and thus, may exhibit excellent molding processability.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

Abstract: A method for fingerprint recognition and a fingerprint recognition device are provided. The method includes the following steps. A touch position of a touch panel is obtained as a fingerprint position. A fingerprint recognition operation is performed according to the fingerprint position. Whether the fingerprint recognition operation is successful is determined. In response to determining that the fingerprint recognition operation is not successful, at least one first position of the touch panel as an updated fingerprint position is generated according to the touch position of the touch panel, and the fingerprint recognition operation is performed according to the updated fingerprint position.

Abstract: A memory device and method of making the same, the memory device including bit lines disposed on the substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.

Abstract: A method and an apparatus for allocating a flexible transmission slot in a wireless local area network (LAN) system are disclosed. A flexible transmission slot allocation method of an access point (AP) in a wireless local area network (WLAN) system according to an exemplary embodiment includes transmitting a beacon including a traffic indication map (TIM) bit to a station, receiving a power save poll (PS-Poll) from the station in a slot implicitly allocated by the TIM bit, and transmitting an acknowledgement (ACK) including transmission slot allocation information on downlink data to the station.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A fingerprint sensing device that includes an analog-front-end (AFE) circuit, an analog-to-digital converter (ADC) and a correction circuit is introduced. The AFE circuit generates an image signal, and the ADC converts the image signal to an output digital code. The correction circuit receives a plurality of first output digital codes that are generated by performing a plurality of first fingerprint sensing operations in a plurality of first exposure time periods. The correction circuit is further configured to calculate a second exposure time period for a second fingerprint sensing operation according to the first output digital codes and the first exposure time periods, wherein the fingerprint sensing device performs the second fingerprint operation in the second exposure time period to generate a second output digital code.

Abstract: A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves, a first material property of the first region varies in a thickness direction of the polishing pad, each of the plurality of first grooves extends through at least two variations in the first material property, and the first material property comprises porosity, specific gravity or absorbance. The method further includes spreading the slurry across a second region of the polishing pad at a second rate different from the first rate, wherein the second region comprises a plurality of second grooves.

Abstract: The present application provides a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region, and including a first recess extending into the semiconductor substrate and disposed in the array region; an isolation structure surrounded by the semiconductor substrate and disposed in the peripheral region; and a word line disposed within the first recess, wherein the word line includes an insulating layer conformal to the first recess and a conductive member surrounded by the insulating layer, and the conductive member includes a second recess extending into the conductive member and toward the semiconductor substrate. A method of manufacturing the memory device is also disclosed.

Abstract: A memory structure, device, and method of making the same, the memory structure including: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; a gate electrode surrounding the high-k dielectric layer; and a memory cell electrically connected to the drain electrode and a bit line. The memory cell includes a first electrode that is electrically connected to the drain electrode.

Abstract: The present application provides a method for manufacturing a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The method includes providing a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region; forming a first recess extending into the semiconductor substrate and disposed in the array region; and forming a word line disposed within the first recess. The formation of the word line includes disposing an insulating layer conformal to the first recess, and forming a conductive member surrounded by the insulating layer and having a second recess extending into the conductive member and toward the semiconductor substrate.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.

Abstract: A polyolefin-polystyrene-based multiblock copolymer and method of making the same are disclosed herein. In some embodiments, a polyolefin-polystyrene-based multiblock copolymer satisfies conditions (a) a weight average molecular weight is 100,000 to 300,000 g/mol; (b) molecular weight distribution is 1.5 to 3.0; (c) measured results of gel permeation chromatography, a graph having an x-axis of log Mw and a y-axis of dw/dlog Mw, are fit to a Gaussian function, where all constants satisfy ?0.01<A<0.03, 4.8<B<5.2, 0.8<C<1.2, and 0.6<D<1.2; and (d) a polyolefin block comprises one or more branch points, where a carbon atom at the branch point is represented by a peak of 36 to 40 ppm, and a terminal carbon atom of a branched chain from the branch point is represented by a peak of 13 to 15 ppm.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate. At least two thin-film transistors (TFT) are disposed over the substrate and electrically coupled to each other in parallel and a magnetoresistive random-access memory (MRAM) cell electrically couples to the thin-film transistors.

Abstract: A semiconductor package includes a substrate and a first semiconductor chip on the substrate and having a first sidewall and a second sidewall different from the first sidewall. A second semiconductor chip is on the substrate and is laterally spaced apart from the first semiconductor chip. A molding layer is on the substrate and between the first sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer exposes the second sidewall of the first semiconductor chip.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.

Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; an active layer disposed above the gate electrode; source/drain electrodes disposed above the gate electrode and separated by the active layer; and at least two dielectric layers disposed between the gate electrode and the source/drain electrodes.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.