Patents by Inventor Jung Yu

Jung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11583926
    Abstract: A radiation beam field shaping device is made from a 3D printed frame that contains and gives shape to a granular material with bulk density of at least 3 g/cm3 and composed of metal grains having a size between 1 ?m and 4 mm. The frame has a hole in the bottom with surrounding walls that defines the desired beam shape. In one implementation, the metal grains are composed of solid tungsten alloy ball bearings and/or tungsten alloy powder.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 21, 2023
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Shu-Jung Yu, Lawrie Basil Skinner, Benjamin Pooya Fahimian
  • Patent number: 11581366
    Abstract: A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • Patent number: 11575043
    Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Yin, Chia-Jung Yu, Pin-Cheng Hsu, Chung-Te Lin
  • Publication number: 20230024174
    Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Yin, Chia-Jung Yu, Pin-Cheng Hsu, Chung-Te Lin
  • Publication number: 20230022020
    Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Yin, Chia-Jung Yu, Pin-Cheng Hsu, Chung-Te Lin
  • Publication number: 20230016367
    Abstract: A method for fingerprint recognition and a fingerprint recognition device are provided. The method includes the following steps. A touch position of a touch panel is obtained as a fingerprint position. A fingerprint recognition operation is performed according to the fingerprint position. Whether the fingerprint recognition operation is successful is determined. In response to determining that the fingerprint recognition operation is not successful, at least one first position of the touch panel as an updated fingerprint position is generated according to the touch position of the touch panel, and the fingerprint recognition operation is performed according to the updated fingerprint position.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Applicant: Novatek Microelectronics Corp.
    Inventor: Jung-Yu Tsai
  • Patent number: 11537236
    Abstract: The fingerprint sensing device that includes a first analog front end (AFE) circuit, a compensation circuit, a correction circuit and an output circuit is introduced. The AFE circuit generates a first image signal according to the fingerprint data read from the plurality of rows of the fingerprint sensor. The correction circuit receives a first output digital code that is generated by reading a predetermined row among the plurality of rows of the fingerprint sensor, and calculates a brightness correction value and a relative illumination (RI) correction value according to the first output digital code. The compensation circuit modifies the first image signal according to the brightness correction value and the RI correction value to generate a second image signal. The output circuit is configured to generate a second output digital code according to the second image signal.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: December 27, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Min Huang, Jung-Yu Tsai
  • Publication number: 20220389256
    Abstract: A digital printed fabric includes a base cloth and a digital printing ink disposed on the base cloth, and a manufacturing method for the digital printing ink includes the following steps. A first thermal process including mixing a dye, a crosslinking agent, and a polyol is performed, such that a polymer dye is formed, in which a reaction temperature of the first thermal process is between 70° C. and 90° C. A second thermal process including mixing the polymer dye and an aqueous bridging agent is performed, such that a first mixture is formed, in which a reaction temperature of the second thermal process is between 90° C. and 120° C. A third thermal process including mixing the first mixture and a chain extender is performed, such that the digital printing ink is formed, in which a reaction temperature of the third thermal process is between 120° C. and 150° C.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 8, 2022
    Inventors: Sun-Wen JUAN, Chun-Hung LIN, Jung-Yu TSAI, Chia-Yi LIN
  • Patent number: 11512996
    Abstract: The present application discloses a flow speed detection circuit and a related chip and flow meter. The flow speed detection circuit includes: a transmitter, configured to provide a front signal and a main signal to a first transducer, wherein the first transducer transforms the front signal and the main signal into a transduced signal to a second transducer, the second transducer transforms the transduced signal into a receiving front signal and a receiving main signal to a receiver; and the receiver includes: a front signal detection circuit, configured to enable the main signal processing circuit after the receiving front signal; and the main signal processing circuit, configured to determine the flow speed based on the receiving main signal after being enabled.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 29, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Jung-Yu Chang
  • Publication number: 20220372289
    Abstract: A hybrid crosslinked polymeric membrane and a process for fabricating the same are provided. Specifically, the hybrid crosslinked polymer membrane comprises a glassy polymer and a ladder-structured polysilsesquioxane and has a crosslinked structure. The hybrid crosslinked polymer membrane can have an excellent permeability of carbon dioxide by virtue of an increase in the free volume and enhanced plasticization resistance, chemical resistance, and durability.
    Type: Application
    Filed: March 22, 2022
    Publication date: November 24, 2022
    Applicant: SOGANG UNIVERSITY RESEARCH & BUSINESS DEVELOPMENT FOUNDATION
    Inventors: Jong Suk LEE, Hyun Jung YU, Ju Ho SHIN, Heseong AN
  • Publication number: 20220355437
    Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Bin HSU, Ren-Guei LIN, Feng-Inn WU, Sheng-Chen WANG, Jung-Yu LI
  • Publication number: 20220344202
    Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.
    Type: Application
    Filed: November 10, 2021
    Publication date: October 27, 2022
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Publication number: 20220344504
    Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
    Type: Application
    Filed: November 10, 2021
    Publication date: October 27, 2022
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Patent number: 11475705
    Abstract: A method for fingerprint recognition and a fingerprint recognition device are provided. The method includes the following steps. A touch position of a touch panel is obtained as a fingerprint position. A fingerprint recognition operation is performed according to the fingerprint position. Whether the fingerprint recognition operation is successful is determined. In response to determining that the fingerprint recognition operation is not successful, at least one first position of the touch panel as an updated fingerprint position is generated according to the touch position of the touch panel, and the fingerprint recognition operation is performed according to the updated fingerprint position.
    Type: Grant
    Filed: December 6, 2020
    Date of Patent: October 18, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventor: Jung-Yu Tsai
  • Publication number: 20220328501
    Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.
    Type: Application
    Filed: November 10, 2021
    Publication date: October 13, 2022
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Publication number: 20220328445
    Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.
    Type: Application
    Filed: December 30, 2021
    Publication date: October 13, 2022
    Inventor: HAE-JUNG YU
  • Patent number: 11463293
    Abstract: An apparatus and method for orthogonal frequency division multiplexing (OFDM) transmission in a wireless local area network (WLAN) system is disclosed, in which the apparatus for OFDM transmission in the WLAN system includes a signal repetition unit to repeat an encoded signal based on a block unit and output the encoded signal and a repeated signal, an interleaver to interleave the encoded signal and the repeated signal and output an interleaved signal, a modulator to modulate the interleaved signal and output modulated symbols, and a phase rotation unit to phase shift the modulated symbol.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 4, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hee Jung Yu, Min Ho Cheong, Jae Seung Lee, Hyoung Jin Kwon, Sok Kyu Lee
  • Publication number: 20220288802
    Abstract: A hole puncher is provided, including: a frame, including a base and a guide portion, the base including at least one punching hole, the guide portion including at least one guide hole corresponding to the at least one punching hole, there being a distance between the punching hole and the guide hole; an operating lever, provably connected to the frame; at least one punching rod, driven by the operating lever, being relatively movable within the at least one guide hole and movable to come within or out from the at least one punching hole, each punching rod including a first straight section, a second straight section and a tapered section which is tapered from the first straight section toward the second straight section.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Inventors: Jung-Yu WANG, Chia-Tse CHEN
  • Patent number: 11441933
    Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein there is a distance greater than zero between the first transducer and the second transducer, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer; the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 13, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Jung-Yu Chang
  • Patent number: 11428555
    Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer have a distance greater than zero, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer, the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 30, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY
    Inventors: Jung-Yu Chang, Yen-Yin Huang