Patents by Inventor Junji Ogawa

Junji Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8972651
    Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: March 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Patent number: 8949511
    Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: February 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ishikawa, Koji Sonoda, Go Uehara, Junji Ogawa, Hideyuki Koseki
  • Patent number: 8898545
    Abstract: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
  • Publication number: 20140321208
    Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.
    Type: Application
    Filed: July 11, 2014
    Publication date: October 30, 2014
    Applicant: HITACHI, LTD.
    Inventors: Atsushi KAWAMURA, Junji OGAWA
  • Publication number: 20140304451
    Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 9, 2014
    Applicant: HITACHI, LTD.
    Inventors: Tsukasa Shibayama, Akifumi Suzuki, Nobuhiro Maki, Junji Ogawa, Masayasu Asano
  • Publication number: 20140297697
    Abstract: The method includes (A) acquiring storage location information that can identify a volume that stores data and access type information, (B) acquiring volume management information that can identify the storage unit that stores the volume, (C) identifying the volume of data to be accessed, identifying the storage unit storing the volume, and identifying the storage method of the storage unit, (D) identifying the type of access to the data to be accessed, (E) determining whether the data needs to be moved to another storage unit of a different storage method based on the storage method and the type of access, and (F) giving an indication of moving the data if it is determined that the data needs to be moved in (E).
    Type: Application
    Filed: July 11, 2012
    Publication date: October 2, 2014
    Applicant: HITACHI, LTD.
    Inventors: Satoru Watanabe, Junji Ogawa
  • Publication number: 20140281064
    Abstract: A shared device unit, which comprises a storage device, is coupled to a plurality of storage systems. The shared device unit provides a plurality of storage areas, which are based on the storage device, to the plurality of storage systems. Each storage system stores allocation management information which comprises an ID of a storage area provided to thereof among the plurality of storage areas, and provides the storage area corresponded to the ID included in the allocation management information to the host computer coupled thereto among the plurality of host computers.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Miho Imazaki, Shigeo Homma, Hiroaki Akutsu, Yoshiaki Eguchi, Akira Yamamoto, Junji Ogawa
  • Patent number: 8832371
    Abstract: A storage system having multiple flash memory packages including flash memory chips and package controllers for controlling access to the flash memory chips is configured such that the package controller receives from a higher-level apparatus, which sends a write request, frequency prediction information that enables prediction of an update frequency with respect to data, which is to be a write target, and when writing data for which a write request has been issued from the higher-level apparatus, control is executed such that data, which is predicted to have a relatively high update frequency based on the frequency prediction information, is preferentially stored in a physical block with the large remaining number of erases in a flash memory chip of flash memory package of the package controller, or such that data, which is predicted to have a relatively low update frequency based on the frequency prediction information, is preferentially stored in a physical block with the small remaining number of erases i
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: September 9, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Go Uehara, Koji Sonoda, Junji Ogawa
  • Publication number: 20140250271
    Abstract: A first storage system comprises a first RAID group comprising multiple first storage devices, which constitute the basis of a first logical volume. A second storage system comprises a second RAID group comprising multiple second storage devices, which constitute the basis of a second logical volume. The RAID configuration of the first RAID group and the RAID configuration of the second RAID group are the same, and the type of a compression/decompression function of the respective first storage devices and the type of a compression/decompression function of the respective second storage devices are the same. Compressed data is read from a first storage device without being decompressed with respect to the data inside a first logical volume, and the read compressed data is written to a second storage device, which is in the same location in RAID in the second RAID group as the location in RAID of this first storage device.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: HITACHI, LTD.
    Inventors: Junichi HARA, Junji OGAWA
  • Patent number: 8806108
    Abstract: A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Junji Ogawa
  • Patent number: 8799562
    Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Publication number: 20140195722
    Abstract: The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area. And when the package processor receives journal data creation command form the processor, allocates the first physical area to second journal area for journal data without storing journal data corresponding to the write data.
    Type: Application
    Filed: January 7, 2013
    Publication date: July 10, 2014
    Applicant: HITACHI, LTD.
    Inventors: Kohei Tatara, Akira Yamamoto, Junji Ogawa
  • Publication number: 20140189203
    Abstract: A cache memory (CM) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The CM comprises a nonvolatile semi-conductor memory (NVM), and provides a logical space to the controller. The controller is configured to partition the logical space into multiple segments and to manage these segments, and to access the CM by specifying a logical address of the logical space. The CM receives the logical address-specified access, and accesses a physical area allocated to a logical area, which belongs to the specified logical address. A first management unit, which is a unit of a segment, is larger than a second management unit, which is a unit of an access performed with respect to the NVM. The capacity of the logical space is larger than the storage capacity of the NVM.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Junji Ogawa, Akira Yamamoto
  • Patent number: 8762638
    Abstract: A first storage system comprises a first RAID group comprising multiple first storage devices, which constitute the basis of a first logical volume. A second storage system comprises a second RAID group comprising multiple second storage devices, which constitute the basis of a second logical volume. The RAID configuration of the first RAID group and the RAID configuration of the second RAID group are the same, and the type of a compression/decompression function of the respective first storage devices and the type of a compression/decompression function of the respective second storage devices are the same. Compressed data is read from a first storage device without being decompressed with respect to the data inside a first logical volume, and the read compressed data is written to a second storage device, which is in the same location in RAID in the second RAID group as the location in RAID of this first storage device.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: June 24, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Hara, Junji Ogawa
  • Publication number: 20140115235
    Abstract: A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Inventors: Yuji Ito, Junji Ogawa, Hideyuki Koseki
  • Publication number: 20140025990
    Abstract: Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Inventors: Hiroaki Akutsu, Junji Ogawa
  • Publication number: 20130311707
    Abstract: A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk. The association unit changes the association by changing the association information in accordance with a state of the nonvolatile semiconductor memory, and identifies based on the association information a physical storage area corresponding to a logical storage area specified in an input/output request from a computer. The execution unit executes the input/output request with respect to the identified physical storage area.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Publication number: 20130311854
    Abstract: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Inventors: Takashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
  • Patent number: 8539142
    Abstract: Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Junji Ogawa, Atsushi Kawamura
  • Patent number: D722642
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 17, 2015
    Assignee: Keyence Corporation
    Inventors: Hiroki Wada, Junji Ogawa