Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

Abstract: Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

Abstract: A method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. The first spacer and the second spacer are next to each other with a space in between. The dielectric layer is etched to form an opening in the dielectric layer, with the opening being overlapped by the space, and with the first spacer and the second spacer being used as a part of an etching mask in the etching. A conductive material is filled into the opening. A planarization process is performed on the conductive material.

Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature.

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.

Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer, a first metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a second metallization pattern. The first metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer, in which the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer. The memory cell is over the metal-containing compound layer and including a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The second metallization pattern extends through the portion of the etch stop layer to the first metallization pattern.

Abstract: Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.