Patents by Inventor Kaan Oguz

Kaan Oguz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230087624
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Kaan OGUZ, I-Cheng TUNG, Chia-Ching LIN, Sou-Chi CHANG, Matthew V. METZ, Uygar E. AVCI, Arnab SEN GUPTA
  • Publication number: 20230086080
    Abstract: In one embodiment, an apparatus includes a magnet, a first structure, and a second structure. The first structure includes a first conductive trace and a magnetoelectric material. The first conductive trace is coupled to an input voltage terminal, and the magnetoelectric material is coupled to the first conductive trace and the magnet. The second structure includes a superlattice structure and a second conductive trace. The superlattice structure includes one or more topological insulator materials. Moreover, the superlattice structure is coupled to the magnet and the second conductive trace, and the second conductive trace is coupled to an output voltage terminal.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Dmitri Evgenievich Nikonov, Ian Alexander Young, John J. Plombon, Hai Li, Kaan Oguz, Tanay A. Gosavi, Emily Walker
  • Publication number: 20230065198
    Abstract: A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Chia-Ching Lin, Tanay A. Gosavi, Ashish Verma Penumatcha, Kaan Oguz, Punyashloka Debashis
  • Patent number: 11594673
    Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Tofizur Rahman, Rohan Patil, Nafees Kabir, Michael Christenson, Ian Young, Hui Jae Yoo, Christopher Wiegand
  • Patent number: 11575083
    Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Ian Young, Dmitri Nikonov, Chia-Ching Lin
  • Patent number: 11574666
    Abstract: A memory device includes a spin orbit electrode structure having a dielectric structure including a first sidewall, a second sidewall opposite to the first sidewall, a top surface. The spin orbit electrode structure further includes an electrode having a spin orbit material adjacent to the dielectric structure, where the electrode has a first electrode portion on the top surface, a second electrode portion adjacent to the first sidewall and a third electrode portion adjacent to the second sidewall. The first electrode portion, the second electrode portion and the third electrode portion are contiguous. The spin orbit electrode structure further includes a conductive interconnect in contact with the second electrode portion or the third electrode portion. The memory device further includes a magnetic junction device on a portion of the top surface of the first electrode portion.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Kaan Oguz, Ian Young
  • Patent number: 11557629
    Abstract: A spin orbit memory device includes a material layer stack on a spin orbit electrode. The material layer stack includes a magnetic tunnel junction (MTJ) and a synthetic antiferromagnetic (SAF) structure on the MTJ. The SAF structure includes a first magnet structure and a second magnet structure separated by an antiferromagnetic coupling layer. The first magnet structure includes a first magnet and a second magnet separated by a single layer of a non-magnetic material such as platinum. The second magnet structure includes a stack of bilayers, where each bilayer includes a layer of platinum on a layer of a magnetic material such.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Christopher Wiegand, Noriyuki Sato, Angeline Smith, Tanay Gosavi
  • Patent number: 11508903
    Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Angeline Smith, Ian Young, Kaan Oguz, Sasikanth Manipatruni, Christopher Wiegand, Kevin O'Brien, Tofizur Rahman, Noriyuki Sato, Benjamin Buford, Tanay Gosavi
  • Patent number: 11502188
    Abstract: An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Dmitri Nikonov, Ian A. Young, Benjamin Buford, Tanay Gosavi, Kaan Oguz, John J. Plombon
  • Patent number: 11476412
    Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Noriyuki Sato, Kevin O'Brien, Benjamin Buford, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • Patent number: 11462678
    Abstract: A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Charles Kuo, Mark Doczy, Noriyuki Sato
  • Publication number: 20220310901
    Abstract: Spin orbit torque (SOT) devices with topological insulator (TI) and heavy metal insert are described. In an example, an integrated circuit structure includes a spin orbit coupling (SOC) interconnect including a TI material. A magnetic layer is above the SOC interconnect. An insert layer includes a heavy metal between and in contact with the TI material and the magnetic layer.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: Kaan OGUZ, Tanay GOSAVI, Emily WALKER, Chia-Ching LIN, Ian A. YOUNG
  • Publication number: 20220310147
    Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Benjamin Buford, Kaan Oguz, John J. Plombon, Ian A. Young
  • Patent number: 11444237
    Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Tanay Gosavi, Gary Allen, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young, Ben Buford
  • Patent number: 11437567
    Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Justin Brockman, Christopher Wiegand, MD Tofizur Rahman, Daniel Ouelette, Angeline Smith, Juan Alzate Vinasco, Charles Kuo, Mark Doczy, Kaan Oguz, Kevin O'Brien, Brian Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11430942
    Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Gary Allen
  • Patent number: 11430943
    Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Patent number: 11417830
    Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Gary Allen, Kaan Oguz, Kevin O'Brien, Noriyuki Sato, Ian Young, Dmitri Nikonov
  • Patent number: 11404630
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Md Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Justin S. Brockman, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11393515
    Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Benjamin Buford, Kaan Oguz, John J. Plombon, Ian A. Young