Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.

Abstract: Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.

Abstract: A method for automatically regulating an explicit congestion notification (ECN) of a data center network based on multi-agent reinforcement learning is provided. The method specifically includes steps 1 to 3. In step 1, an ECN threshold regulation of a data center network is modelled as a multi-agent reinforcement learning problem. In step 2, an independent proximal policy optimization (IPPO) algorithm in multi-agent reinforcement learning is used for training according to features of the data center network. In step 3, offline pre-training is combined with online incremental learning such that a model deployed on each switch is capable of rapidly adapting to a dynamic data center network environment.

Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.

Abstract: An anaerobic-AO-SACR combined advanced nitrogen removal system for high ammonia-nitrogen wastewater, in which high ammonia-nitrogen wastewater first enters an anaerobic reactor to remove most of organic matters from the wastewater, effluent water enters an AO reactor for nitrogen removal by pre-denitrification in an anoxic zone and for removal of the remaining organic matters and nitrification of ammonia nitrogen in an aerobic zone, and then the effluent water enters an intermediate pool. Meanwhile, under the control of a water quality testing device and a PLC controller, a part of raw water is introduced into the intermediate pool to adjust the carbon nitrogen ratio of the wastewater.

Abstract: Disclosed is a semiconductor structure, including a substrate; a V-shaped groove layer, a V-shaped groove enlargement layer and a semiconductor epitaxial layer stacked from bottom to top; a first V-shaped groove arranged on a surface of the V-shaped groove layer close to the V-shaped groove enlargement layer; a second V-shaped groove arranged on a surface of the V-shaped groove enlargement layer close to the semiconductor epitaxial layer, where a size of the second V-shaped groove is greater than a size of the first V-shaped groove In the present disclosure, a lateral epitaxy effect of the V-shaped groove enlargement layer and the semiconductor epitaxial layer is realized for two times, which makes dislocation fully bend, effectively improving crystal quality. Meanwhile, the first V-shaped groove and the second V-shaped groove are self-formed during an epitaxial growth process, which greatly reduces preparation cost and improves preparation efficiency.

Abstract: In the present disclosure, a semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes a base, a first mask layer, a first epitaxial layer, and a second epitaxial layer. The first mask layer is located on the base, and the first mask layer has a first window that exposes the base. The first window includes an opening end far from the base and a bottom wall end close to the base. On the plane where the base is located, the orthographic projection of the opening end falls within the bottom wall end.

Abstract: A light emitting device includes: a substrate; a DBR mask layer on a side of the substrate, the DBR mask layer being provided with a window exposing the substrate, the window including an opening end away from the substrate and a bottom wall end close to the substrate, and on a plane where the substrate is located, an orthographic projection of the opening end falling within an orthographic projection of the bottom wall end; and a light emitting unit. The light emitting unit includes an active layer located on a side, away from the substrate, of the DBR mask layer. Providing the window on the DBR mask layer may reduce dislocation density during epitaxial growth of the light emitting unit, and arrangement of the DBR mask layer may improve light extraction efficiency of the light emitting device.

Abstract: An epitaxial structure of a light-emitting device and a manufacturing method thereof are provided. The epitaxial structure of the light-emitting device includes a first semiconductor layer, an active region and a second semiconductor layer sequentially stacked; where the active region includes at least one group of a barrier layer and a quantum well layer which are stacked, a surface of the quantum well layer away from the first semiconductor layer has a first roughness, a surface of the barrier layer away from the first semiconductor layer has a second roughness, and the first roughness is greater than the second roughness.

Abstract: The present disclosure provides a semiconductor structure, including: a substrate, a first-type mask layer, a second-type mask layer, and an epitaxial layer; where the first-type mask layer includes a first mask multilayer, the first mask multilayer includes a first mask layer and a second mask layer, the first mask layer includes a first window, the second mask layer includes a second window communicating with the first window, the second window and the first window constitute a first-type window, and a cross-section of the second window is larger than that of the first window; the second-type mask layer is located on a side of the first-type mask layer away from the base; the second-type mask layer includes a second-type window communicating with the first-type window, and a cross-section of the second-type window is smaller than that of the second window.

Abstract: Disclosed is an image sensor, comprising: at least one photosensitive unit, where the photosensitive unit includes a main photosensitive region and an auxiliary photosensitive region arranged at the periphery of the main photosensitive region, and a photosensitive component content of the main photosensitive region is different from a photosensitive component content of the auxiliary photosensitive region. The disclosure enlarges a wavelength range of sensible light of each the photosensitive unit by arranging the auxiliary photosensitive region at the periphery of the main photosensitive region of the photosensitive unit, where the photosensitive component content of the main photosensitive region is different from that of the auxiliary photosensitive region. Thereby more image details may be recorded to generate images with high dynamic range, which enables people to experience a visual effect close to a real environment.

Abstract: A computer-implemented framework and/or system for cyberbullying detection is disclosed. The system includes two main components: (1) A representation learning network that encodes the social media session by exploiting multi-modal features, e.g., text, network, and time; and (2) a multi-task learning network that simultaneously fits the comment inter-arrival times and estimates the bullying likelihood based on a Gaussian Mixture Model. The system jointly optimizes the parameters of both components to overcome the shortcomings of decoupled training. The system includes an unsupervised cyberbullying detection model that not only experimentally outperforms the state-of-the-art unsupervised models, but also achieves competitive performance compared to supervised models.

Abstract: A semiconductor structure is provided, and comprises: a substrate, an insulation layer and a protruding structure. The insulation layer is located on the substrate, and the protruding structure protrudes from the insulation layer, where the protruding structure further includes a first heterojunction structure, a second heterojunction structure, . . . , and an n-th heterojunction structure that are sequentially stacked in a direction away from the substrate, and n is greater than or equal to 2, wherein the first heterojunction structure includes a first channel layer and a first barrier layer, the second heterojunction structure includes a second channel layer and a second barrier layer, . . . , and the n-th heterojunction structure includes an n-th channel layer and an n-th barrier layer, and component proportions of at least two of the first barrier layer, the second barrier layer, . . . , or the n-th barrier layer are different.

Abstract: Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.

Abstract: The present disclosure provides a semiconductor structure including a substrate, an insulation layer on the substrate; a protrusion structure protruding out of the insulation layer, where the protrusion structure includes a source region, a drain region and a channel region between whereof; the protrusion structure includes a first heterojunction structure, . . . and an n-th heterojunction structure sequentially stacked along a direction away from the substrate, where n is an integer greater than or equal to 2; the first heterojunction structure includes a first channel layer and a first barrier layer, . . . the n-th heterojunction structure includes an n-th channel layer and an n-th barrier layer, and at least one of the first barrier layer, . . . or the n-th barrier layer is doped with an N-type element; the source electrode on the source region, the drain electrode on the drain region, and the gate structure on the channel region.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method of the semiconductor, including: a first semiconductor layer, where first protrusions are at a first surface of the first semiconductor layer; and a second semiconductor layer on the first semiconductor layer, where second protrusions are at a surface of the second semiconductor layer away from the first semiconductor layer, the second protrusions correspond to the first protrusions. A conductivity type of the second semiconductor layer is the same as a conductivity type of the first semiconductor layer, and a doping concentration of the second semiconductor layer is lower than a doping concentration of the first semiconductor layer. The third semiconductor layer is on the second semiconductor layer, and a conductivity type of the third semiconductor layer is opposite to the conductivity type of the first semiconductor layer.

Abstract: The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate is etched from a front surface to form a trench. Then, a P-type semiconductor layer and an N-type semiconductor layer are sequentially formed on a bottom wall and side walls of the trench and the front surface of the semiconductor substrate. The trench is partially filled with the P-type semiconductor layer. Thereafter, the N-type semiconductor layer and the P-type semiconductor layer are planarized, and the P-type semiconductor layer and the N-type semiconductor layer in the trench are retained. Next, a gate structure is formed at a gate area of the front surface of the semiconductor substrate, a source electrode is formed on two sides of the gate structure, and a drain electrode is formed on a rear surface of the semiconductor substrate respectively.

Abstract: A portable information handling system supports a flexible OLED display film over housing portions rotationally coupled by a hinge by folding the OLED display film over the hinge. Hinge brackets that couple to the housing portions each have a gear member with a semicircular shape gear inner circumference that engages a gear subassembly of the hinge main body. Hinge bracket rotation translates through the gear subassembly for synchronized housing rotation. The hinge main body has first and second semicircular portions with a smooth surface defined to accept the outer circumference smooth surface of the gear member semicircular shape at first and second rotation axes about which the hinge brackets pivot so that the display film has space to fold in the closed position.

Abstract: A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.