Patents by Inventor Kai D. Feng
Kai D. Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985615Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.Type: GrantFiled: February 1, 2017Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
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Patent number: 9818652Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.Type: GrantFiled: April 27, 2016Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Chengwen Pei, Ping-Chuan Wang, Kai D. Feng
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Publication number: 20170316986Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Chengwen Pei, Ping-Chuan Wang, Kai D. Feng
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Publication number: 20170317166Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Chengwen Pei, Hanyi Ding, Ping-Chuan Wang, Kai D. Feng
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Patent number: 9768110Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: GrantFiled: March 4, 2016Date of Patent: September 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9721854Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.Type: GrantFiled: December 5, 2012Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20170141771Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.Type: ApplicationFiled: February 1, 2017Publication date: May 18, 2017Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
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Patent number: 9391014Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: GrantFiled: August 13, 2015Date of Patent: July 12, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20160190005Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9380688Abstract: Aspects relate to an electrostatic discharge (ESD) system for ESD protection and a method of manufacturing. The ESD system includes a lower substrate, an underfill layer that is disposed on the lower substrate that includes a plurality of cavities, and an upper substrate disposed on the underfill layer. The upper substrate includes a plurality of air ventilation shafts. The ESD system also includes a plurality of air gap metal tip structures disposed within one or more of the plurality of cavities in the underfill, wherein the plurality of ventilation shafts line up with the plurality of air gap metal tip structures. At least one air gap tip structure includes an upper metallic tip and a lower metallic tip that are placed along a vertical axis that is perpendicular to the substrates. An air cavity is provided between the upper metallic tip and the lower metallic tip forming an air chamber.Type: GrantFiled: December 31, 2015Date of Patent: June 28, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Yang Liu, Dongbing Shao, Zheng Xu
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Patent number: 9331012Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: GrantFiled: March 8, 2012Date of Patent: May 3, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20160071742Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: ApplicationFiled: November 16, 2015Publication date: March 10, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9281236Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: GrantFiled: May 21, 2015Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9240406Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.Type: GrantFiled: April 21, 2014Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun, Richard A. Wachnik, Ping-Chuan Wang
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Patent number: 9217769Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.Type: GrantFiled: October 9, 2012Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Hailing Wang, Zhijian Yang
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Publication number: 20150348899Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9190360Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: GrantFiled: February 17, 2014Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150303191Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.Type: ApplicationFiled: April 21, 2014Publication date: October 22, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun, Richard A. Wachnik, Ping-Chuan Wang
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Patent number: 9166588Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.Type: GrantFiled: January 20, 2014Date of Patent: October 20, 2015Assignee: GLOBALFOUNDIRES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian J. Yang
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Publication number: 20150255326Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang