Abstract: Provided are a lane line recognition method, an electronic device and a storage medium, relating to a technical field of artificial intelligence, in particular to technical fields of intelligent transportation, automatic driving and deep learning. The lane line recognition method includes: extracting a basic feature of an original image; recognizing at least one lane line node in the original image by using the basic feature of the original image; extracting a local feature from the basic feature of the original image by using the at least one lane line node; fusing the basic feature and the local feature; and recognizing a lane line in the original image based on a fused result.

Abstract: Embodiments of the present disclosure relate to projection stabilization systems and maskless lithography systems having projection stabilization systems. The projection stabilization system compensates for propagating vibrations that move image projection systems (IRS's). The IRS's are in a processing positon prior to operation of the maskless lithography process. One or more stiffeners are coupled to the IPS. The one or more stiffeners apply pressure to flexures coupled to each stiffener. The flexures are coupled to the IPS to provide stabilization to the IPS during the operations of the maskless lithography process. For example, the one or more of stiffeners protect the IPS from vibrations that propagate through the system during operation.

Abstract: A display panel and a display device; the display panel includes a plurality of bonding pins. At least one bonding pin includes a first bonding electrode disposed on a side of an insulating layer group away from a base substrate, the insulating layer group having a first concave portion, the first bonding electrode having a second concave portion, an orthographic projection of the second concave portion on the base substrate being located within an orthographic projection of the first concave portion on the base substrate. The first bonding electrode includes at least a first conductor layer and a second conductor layer, and the at least one bonding pin further includes a filling portion disposed on a side of the second concave portion away from the base substrate, which is at least partially within the second concave portion.

Abstract: An integrated optical component coupled to a circuit board of an aerosol sensor is provided. The integrated optical component comprising a medium including a first, second plane, third plane, wherein the first plane is adjacent to a detection area, the second plane is positioned about a photosensor, and the third plane is opposite an angle formed by an intersection of the first and second plane. The integrated optical component further comprising a first lens configured on the first sidewall, the first lens configured to receive incident light from the detection area and focus the incident light onto a reflector through the medium, the reflector configured on the third sidewall, the reflector configured to reflect the incident light towards a second lens, and the second lens configured on the second sidewall, the second lens configured to receive the incident light from the reflector and focus the incident light to the photosensor.

Abstract: A network node may be configured to transmit a first indication of MIMO assistance information for a UE, where the MIMO assistance information is associated with at least one of a SU-MIMO configuration or a MU-MIMO configuration. The UE may receive the first indication of MIMO assistance information from a network node, perform at least one of an inter-layer IC operation, a CSI reporting operation, or an SRS antenna port switching operation based on at least one of the SU-MIMO configuration or the MU-MIMO configuration, and transmit information associated with at least one of the CSI reporting operation or the SRS antenna port switching operation based on at least one of the SU-MIMO configuration or the MU-MIMO configuration. The network node may obtain the information associated with at least one of a CSI reporting operation or an SRS antenna port switching operation.

Abstract: The present disclosure provides a nap mat. The nap mat includes: a sleep mattress; a pillow, integrally disposed at a first end of the sleep mattress; and a cover blanket, a side of the cover blanket being connected to a side of the sleep mattress, stitches being crossed on the cover blanket, the stitches partitioning an inner space of the cover blanket into a plurality of accommodation chambers, the accommodation chambers being provided with weighted fillers, the weighted fillers being configured to increase a gravity of the cover blanket. With the above configurations, the nap mat according to the present disclosure has good portability and better warmth retention.

Abstract: A method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.

Abstract: A method includes forming first and second fins disposed on a substrate, forming a gate structure over the first and second fins, epitaxially growing a first source/drain (S/D) feature on the first fin and a second S/D feature on the second fin, depositing a dielectric layer covering the first and second S/D features, etching the dielectric layer to form a trench exposing the first and second S/D features, forming a metal structure in the trench and extending from the first S/D feature to the second S/D feature, performing a cut metal process to form an opening dividing the metal structure into a first segment over the first S/D feature and a second segment over the second S/D feature, and depositing an isolation feature in the opening. The isolation feature separates the first segment from the second segment.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.

Abstract: The present application provides a system for unmanned aerial vehicle (UAV) parachute landing. An exemplary system includes a detector configured to detect at least one of a flight speed, a wind speed, a wind direction, a position, a height, and a voltage of a UAV. The system also includes a memory storing instructions and a processor configured to execute the instructions to cause the system to: determine whether to open a parachute of the UAV in accordance with a criterion, responsive to the determination to open the parachute of the UAV, stop a motor of the UAV that spins a propeller of the UAV, and open the parachute of the UAV after stopping the motor of the UAV for a first period.

Abstract: The present invention discloses a method for building a co-culture model for Caco-2/RAW-264.7 cells induced by lipopolysaccharides and an application of the co-culture model. The method includes: 1) culturing Caco-2 cells and RAW-264.7 cells; 2) inoculating the 5 Caco-2 cells onto an AP side of an upper chamber of a Transwell plate, and incubating; 3) inoculating the RAW-264.7 cells onto a 24-well plate, and incubating; 4) transferring the upper chamber of the Transwell plate into the 24-well plate; 5) dissolving lipopolysaccharides in PBS to prepare a stock solution, filtering, and diluting for later use; and 6) adding an LPS-10% DMEM medium on a BL side, incubating, and forming an intestinal inflammation model.

Abstract: A vehicle control method, a vehicle control apparatus, an electronic device and a self-driving vehicle all relates to the field of self-driving and intelligent transportation technologies. The method includes: when a vehicle is moving, in a case that an occluding object is detected, determining a hard brake speed limit point and a potential collision point according to a planned path of the vehicle and position information of the occluding object; calculating a speed limit value of the hard brake speed limit point based on a distance between the hard brake speed limit point and the potential collision point; in a case that a planned speed of the vehicle at the hard brake speed limit point is less than or equal to the speed limit value, controlling the vehicle to move at the planned speed.

Abstract: A resin composition and a metal clad substrate are provided. The resin composition includes: 20 phr to 40 phr of an epoxy resin, 40 phr to 60 phr of a modified benzoxazine resin, 2 phr to 10 phr of a maleimide resin, and 25 phr to 50 phr of fillers. The modified benzoxazine resin contains a DOPO group. Based on a total weight of the modified benzoxazine resin being 100 wt %, an amount of the DOPO group ranges from 10 wt % to 20 wt %.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: A heat dissipating system for electronic devices includes a first heat dissipation device, a second heat dissipation device, and a thermal conduction component. The thermal conduction component is disposed around the first heat dissipation device and configured to thermally contact a heat source. The second heat dissipation device is disposed adjacent to the thermal conduction component. The first heat dissipation device is configured to generate a first working fluid toward the thermal conduction component, such that the heat transferred from the heat source to the thermal conduction component is dispersed in a plurality of directions directing away from the first heat dissipation device. The second heat dissipation device is configured to generate a second working fluid, such that the heat distributed adjacent to the second heat dissipation device is dissipated in at least one direction directing away from the second heat dissipation device.

Abstract: The present invention relates to a method and device for preparing an ultrathin metal lithium foil. With regard to the problems of lithium preparation processes in the prior art having a high lithium preparation reaction temperature, a low lithium recovery rate, low purity in collected lithium foils, a complicated process operation, etc., the present invention provides a method for preparing an ultrathin metal lithium foil, wherein firstly, a complex lithium salt is prepared, the complex lithium salt and a reducing agent are then subjected to a vacuum thermal reduction reaction so as to generate a metal vapor, the metal vapor is then subjected to vacuum distillation, and finally, vacuum evaporation is used to prepare the ultrathin metal lithium foil of the present invention.

Abstract: Systems and methods are disclosed herein for detecting impurities of harvested plants in a receptacle of a harvester. In an embodiment, a harvester controller receives, from a camera facing the contents of the receptacle, an image of the contents. The harvester controller applies the image as input to a machine learning model. The harvester controller receives, as output from the machine learning model, an identification of an impurity of the harvested plants. The harvester controller transmits a control signal based on the impurity.

Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.