Abstract: A rack temperature controlling method includes performing the following operations through a controller: obtaining a rack temperature data, calculating a temperature variant according to the rack temperature data, calculating a temperature deviation according to the temperature variant and a reference temperature, calculating a target speed according to the temperature deviation, and adjusting a speed of a fan to the target speed. A rack temperature controlling system including a thermometer and a controller is further provided. The thermometer measures and outputs a rack temperature data. The controller receives the rack temperature data, and calculates a temperature variant according to the rack temperature data. The controller further calculates a temperature deviation according to the temperature variant and a reference temperature, calculates a target speed according to the temperature deviation, and adjusts a speed of a fan to the target speed.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

Abstract: A fan control method for controlling a set of fans of a system includes collecting M first sets of characteristic variables of a first period; inputting the M first sets of characteristic variables to a neural network to generate N third sets of characteristic variables of a second period corresponding to a second set of characteristic variables; adjusting the second set of characteristic variables to generate P adjusted second sets of characteristic variables to accordingly generate Q adjusted third sets of characteristic variables; generating an optimized second set of characteristic variables according to the N third sets of characteristic variables and the Q adjusted third sets of characteristic variables; generating a set of weights according to the optimized second set of characteristic variables; and controlling the set of fans according to the set of weights. The first period precedes the second period. M, N, P, Q are positive integers.

Abstract: A cigar cutter having a locking mechanism includes a rotatable ring, an elastic element, a locking assembly and an arresting portion. When a cutting blade unit of the cigar cutter is pressed, the rotatable ring is driven to rotate to compress the elastic element, and the arresting portion will engage with a plate of the locking assembly so that the cigar cutter enters a closed state. When an operation key of the locking assembly is pushed, the plate no longer blocks the arresting portion, and a force of the elastic element will drive the rotatable ring to rotate reversely so that the arresting portion is moved to its original position, thereby keeping the cigar cutter in an open state.

Abstract: Provide crystal forms of 5-fluoro-1-(4-fluoro-3-(4-(pyrimidin-2-yl) piperazine-1-carbonyl) benzyl) quinazoline-2, 4 (1H,3H)-dione and preparation method thereof.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: A heat dissipating system for electronic devices includes a first heat dissipation device, a second heat dissipation device, and a thermal conduction component. The thermal conduction component is disposed around the first heat dissipation device and configured to thermally contact a heat source. The second heat dissipation device is disposed adjacent to the thermal conduction component. The first heat dissipation device is configured to generate a first working fluid toward the thermal conduction component, such that the heat transferred from the heat source to the thermal conduction component is dispersed in a plurality of directions directing away from the first heat dissipation device. The second heat dissipation device is configured to generate a second working fluid, such that the heat distributed adjacent to the second heat dissipation device is dissipated in at least one direction directing away from the second heat dissipation device.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.

Abstract: An air cooling system for electronic devices includes a body, a thermal conduction component, and a heat dissipation fan. The body has a heat dissipation port and air inlet ports. The air inlet ports are disposed at a first housing part and a second housing part of the body. The first housing part is opposite to the second housing part. The thermal conduction component is disposed in the body and configured to contact a heat source. The heat dissipation fan is disposed in the body. The heat dissipation fan includes a first axial air inlet opening, a second axial air inlet opening, and radial air outlet openings. The first axial air inlet opening corresponds to one of the air inlet ports of the first housing part. The second axial air inlet opening corresponds to one of the air inlet ports of the second housing part.

Abstract: A head-mounted display device assembly and an external adjustment module are provided. The head-mounted display device assembly includes a head-mounted display device and the external adjustment module. The head-mounted display device has a first lens and a second lens corresponding to both eyes, and also has a driven mechanism. The first lens and the second lens are respectively coupled to the driven mechanism. The external adjustment module is used for assembling and electrically connecting to the head-mounted display device, and includes a driving element and a transmission element. In a coupling state, the transmission element is coupled to the driving element and the driven mechanism, and the driving element drives the driven mechanism via the transmission element to adjust a distance between the first lens and the second lens. In a separation state, at least one of the driving element and the driven mechanism is separated from the transmission element.

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: A connector assembly for mounting a chip module to a printed circuit board (PCB) includes: a seating mechanism including a socket connector, a metallic seat frame, and a metallic load plate; a back plate; and plural fasteners extending through the seating mechanism, the PCB, and the back plate to fasten the seating mechanism and the back plate on two opposite sides of the PCB, wherein the back plate has a curved inner region and a flat outer region and the fasteners extend through the flat outer region of the back plate.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a method and an apparatus for determining an address mapping relationship, and a storage medium. The method for determining an address mapping relationship includes: obtaining a mapping relationship table between preset addresses and DRAM physical addresses under a preset condition; and analyzing values of bit addresses in the DRAM physical address according to a first preset rule, to determine an attribute of each bit address in the DRAM physical address, where the attribute is used for representing an address field of the DRAM physical address.

Abstract: An immersion cooling system and level control method thereof, comprising: provide a main tank with a first upper/lower level limit and a storage tank with a second upper/lower level limit, the connection site of the main tank is higher than that of the storage tank and the first upper level limit; measure the level of the two tanks; when the level of the main tank is lower than the first lower level limit and the level of the storage tank is higher than the second lower level limit, open a first valve and a pump so that the liquid is input into the main tank; and when the level of the main tank is higher than the first upper level limit and the level of the storage tank is not higher than the second upper level limit, open the second valve to allow liquid to enter the storage tank.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.