Patents by Inventor Kalpendu Shastri
Kalpendu Shastri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060083144Abstract: An improvement in the reliability and lifetime of SOI-based opto-electronic systems is provided through the use of a monolithic opto-electronic feedback arrangement that monitors one or more optical signals within the opto-electronic system and provides an electrical feedback signal to adjust the operation parameters of selected optical devices. For example, input signal coupling orientation may be controlled. Alternatively, the operation of an optical modulator, switch, filter, or attenuator may be under closed-loop feedback control by virtue of the inventive monolithic feedback arrangement. The feedback arrangement may also include a calibration/look-up table, coupled to the control electronics, to provide the baseline signals used to analyze the system's performance.Type: ApplicationFiled: October 19, 2005Publication date: April 20, 2006Inventors: David Piede, Kalpendu Shastri, Robert Montgomery, Prakash Gothoskar, Vipulkumar Patel, Mary Nadeau
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Patent number: 7020364Abstract: A trapezoidal shaped single-crystal silicon prism is formed and permanently attached to an SOI wafer, or any structure including a silicon optical waveguide. In order to provide efficient optical coupling, the dopant species and concentration within the silicon waveguide is chosen such that the refractive index of the silicon waveguide is slightly less than that of the prism coupler (refractive index of silicon?3.5). An intermediate evanescent coupling layer, disposed between the waveguide and the prism coupler, comprises a refractive index less than both the prism and the waveguide. In one embodiment, the evanescent coupling layer comprises a constant thickness. In an alternative embodiment, the evanescent coupling layer may be tapered to improve coupling efficiency between the prism and the waveguide. Methods of making the coupling arrangement are also disclosed.Type: GrantFiled: September 23, 2003Date of Patent: March 28, 2006Assignee: SiOptical Inc.Inventors: Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine A. Yanushefski
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Patent number: 7013067Abstract: An arrangement for coupling between a free-space propagating optical signal and an ultrathin silicon waveguide formed in an upper silicon layer (SOI layer) of a silicon-an-insulator (SOI) structure includes a silicon nanotaper structure formed in the (SOI layer) and coupled to the ultrathin silicon waveguide. A dielectric waveguide coupling layer is disposed so as to overly a portion of a dielectric insulating layer in a region where an associated portion of the SOI layer has been removed. An end portion of the dielectric waveguide coupling layer is disposed to overlap an end section of the silicon nanotaper to form a mode conversion region between the free-space signal and the ultrathin silicon waveguide. A free-space optical coupling arrangement is disposed over the dielectric waveguide coupling layer and used to couple between free space and the dielectric waveguide coupling layer and thereafter into the ultrathin silicon waveguide.Type: GrantFiled: February 9, 2005Date of Patent: March 14, 2006Assignee: SiOptical, Inc.Inventors: Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine A. Yanushefski
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Patent number: 7003196Abstract: A coupling arrangement for allowing multiple wavelengths to be coupled into and out of a relatively thin silicon optical waveguide layer utilizes a diffractive optical element, in the form of a volume phase grating, in combination with a prism coupling structure. The diffractive optical element is formed to comprise a predetermined modulation index sufficient to diffract the various wavelengths through angles associated with improving the coupling efficiency of each wavelength into the silicon waveguide. The diffractive optical element may be formed as a separate element, or formed as an integral part of the coupling facet of the prism coupler.Type: GrantFiled: September 7, 2004Date of Patent: February 21, 2006Assignee: SiOptical, Inc.Inventors: Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine A. Yanushefski
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Patent number: 7000207Abstract: A system and method for providing the layout of non-Manhattan shaped integrated circuit elements using a Manhattan layout system utilizes a plurality of minimal sized polygons (e.g., rectangles) to fit within the boundaries of the non-Manhattan element. The rectangles are fit such that at least one vertex of each rectangle coincides with a grid point on the Manhattan layout system. Preferably, the rectangles are defined by using the spacing being adjacent grid points as the height of each rectangle. As the distance between adjacent grid points decreases, the layout better matches the actual shape of the non-Manhattan element. The system and method then allows for electrical and optical circuit elements to be laid out simultaneously, using the same layout software and equipment.Type: GrantFiled: April 8, 2004Date of Patent: February 14, 2006Assignee: SiOptical, Inc.Inventors: Prakash Gothoskar, Margaret Ghiron, Vipulkumar Patel, Robert Keith Montgomery, Kalpendu Shastri, Soham Pathak, Katherine A. Yanushefski
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Publication number: 20050289490Abstract: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design.Type: ApplicationFiled: June 22, 2005Publication date: December 29, 2005Inventors: Kalpendu Shastri, Soham Pathak, Prakash Gothoskar, Paulius Mosinskis, Bipin Dama
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Patent number: 6980720Abstract: A low loss coupling arrangement between a slab/strip waveguide and a rib waveguide in an optical waveguiding structure formed on a silicon-on-insulator (SOI) platform utilizes tapered sections at the input and/or output of the rib waveguide to reduce loss. Optical reflections are reduced by using silicon tapers (either vertical tapers, horizontal tapers, or two-dimensional tapers) that gradually transition the effective index seen by an optical signal propagating along the slab/strip waveguide and subsequently into and out of the rib waveguide. Loss can be further reduced by using adiabatically contoured silicon regions at the input and output of the rib waveguide to reduce mode mismatch between the slab/strip waveguide and rib waveguide. In a preferred embodiment, concatenated tapered and adiabatic sections can be used to provide for reduced optical reflection loss and reduced optical mode mismatch.Type: GrantFiled: April 5, 2004Date of Patent: December 27, 2005Assignee: SiOptical, Inc.Inventors: Prakash Gothoskar, Margaret Ghiron, Vipulkumar Patel, Robert Keith Montgomery, Kalpendu Shastri, Soham Pathak, Katherine A. Yanushefski
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Patent number: 6968110Abstract: A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.Type: GrantFiled: April 21, 2004Date of Patent: November 22, 2005Assignee: SiOptical, Inc.Inventors: Vipulkumar Patel, Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Kalpendu Shastri, Soham Pathak, Katherine A. Yanushefski
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Publication number: 20050236619Abstract: A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Inventors: Vipulkumar Patel, Margaret Ghiron, Prakash Gothoskar, Robert Montgomery, Kalpendu Shastri, Soham Pathak, Katherine Yanushefski
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Publication number: 20050213873Abstract: An arrangement for providing optical crossovers between waveguides formed in an SOI-based structure utilize a patterned geometry in the SOI structure that is selected to reduce the effects of crosstalk in the area where the signals overlap. Preferably, the optical signals are fixed to propagate along orthogonal directions (or are of different wavelengths) to minimize the effects of crosstalk. The geometry of the SOI structure is patterned to include predetermined tapers and/or reflecting surfaces to direct/shape the propagating optical signals. The patterned waveguide regions within the optical crossover region may be formed to include overlying polysilicon segments to further shape the propagating beams and improve the coupling efficiency of the crossover arrangement.Type: ApplicationFiled: March 24, 2005Publication date: September 29, 2005Inventors: David Piede, Prakash Gothoskar, Margaret Ghiron, Robert Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine Yanushefski
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Publication number: 20050201683Abstract: An arrangement for providing optical coupling between a free-space propagating optical signal and an ultrathin silicon waveguide formed in an upper silicon layer of a silicon-on-insulator (SOI) structure includes a silicon nanotaper structure formed in the upper silicon layer (SOI layer) of the SOI structure and coupled to the ultrathin silicon waveguide. A dielectric waveguide coupling layer, with a refractive index greater than the index of the dielectric insulating layer but less than the refractive index of silicon, is disposed so as to overly a portion of the dielectric insulating layer in a region where an associated portion of the SOI layer has been removed. An end portion of the dielectric waveguide coupling layer is disposed to overlap an end section of the silicon nanotaper to form a mode conversion region between the free-space propagating optical signal and the ultrathin silicon waveguide.Type: ApplicationFiled: February 9, 2005Publication date: September 15, 2005Applicant: SiOptical, Inc.Inventors: Margaret Ghiron, Prakash Gothoskar, Robert Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine Yanushefski
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Publication number: 20050194990Abstract: A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.Type: ApplicationFiled: March 8, 2005Publication date: September 8, 2005Inventors: Prakash Gothoskar, Margaret Ghiron, Robert Montgomery, Vipulkumar Patel, Kalpendu Shastri, Soham Pathak, David Piede, Katherine Yanushefski
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Publication number: 20050189591Abstract: An arrangement for actively controlling, in two dimensions, the manipulation of light within an SOI-based optical structure utilizes doped regions formed within the SOI layer and a polysilicon layer of a silicon-insulator-silicon capacitive (SISCAP) structure. The regions are oppositely doped so as to form an active device, where the application of a voltage potential between the oppositely doped regions functions to modify the refractive index in the affected area and alter the properties of an optical signal propagating through the region. The doped regions may be advantageously formed to exhibit any desired “shaped” (such as, for example, lenses, prisms, Bragg gratings, etc.), so as to manipulate the propagating beam as a function of the known properties of these devices. One or more active devices of the present invention may be included within a SISCAP formed, SOI-based optical element (such as, for example, a Mach-Zehnder interferometer, ring resonator, optical switch, etc.Type: ApplicationFiled: February 28, 2005Publication date: September 1, 2005Inventors: Prakash Gothoskar, Margaret Ghiron, Robert Montgomery, Vipulkumar Patel, Kalpendu Shastri, Soham Pathak, Katherine Yanushefski
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Patent number: 6934444Abstract: A practical realization for achieving and maintaining high-efficiency transfer of light from input and output free-space optics to a high-index waveguide of sub-micron thickness is described. The required optical elements and methods of fabricating, aligning, and assembling these elements are discussed. Maintaining high coupling efficiency reliably over realistic ranges of device operating parameters is discussed in the context of the preferred embodiments.Type: GrantFiled: November 24, 2003Date of Patent: August 23, 2005Assignee: SiOptical, Inc.Inventors: Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine A. Yanushefski
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Publication number: 20050179986Abstract: An SOI-based photonic bandgap (PBG) electro-optic device utilizes a patterned PBG structure to define a two-dimensional waveguide within an active waveguiding region of the SOI electro-optic device. The inclusion of the PBG columnar arrays within the SOI structure results in providing extremely tight lateral confinement of the optical mode within the waveguiding structure, thus significantly reducing the optical loss. By virtue of including the PBG structure, the associated electrical contacts may be placed in closer proximity to the active region without affecting the optical performance, thus increasing the switching speed of the electro-optic device. The overall device size, capacitance and resistance are also reduced as a consequence of using PBGs for lateral mode confinement.Type: ApplicationFiled: January 24, 2005Publication date: August 18, 2005Inventors: Prakash Gothoskar, Margaret Ghiron, Robert Montgomery, Vipulkumar Patel, Soham Pathak, David Piede, Kalpendu Shastri, Katherine Yanushefski
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Patent number: 6917730Abstract: An optical coupling system for use with multiple wavelength optical signals provides improved coupling efficiency between a free-space optical beam and a relatively thin, surface layer of an SOI structure (“SOI layer”), allowing for sufficient coupling efficiency (greater than 50%) over a predetermined wavelength range. An evanescent coupling layer, disposed between a coupling prism and an SOI layer, is particularly configured to improve the coupling efficiency. In one embodiment, the thickness of the evanescent layer is reduced below an optimum value for a single wavelength, the reduced thickness improving coupling efficiency over a predetermined wavelength range around a defined center wavelength. Alternatively, a tapered thickness evanescent coupling layer may be used to improve coupling efficiency (or a combination of reduced thickness and tapered configuration).Type: GrantFiled: April 28, 2004Date of Patent: July 12, 2005Assignee: SiOptical, Inc.Inventors: Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Vipulkumar Patel, Soham Pathak, Kalpendu Shastri, Katherine A. Yanushefski
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Publication number: 20050135727Abstract: An SOI-based opto-electronic structure includes various electronic components disposed with their associated optical components within a single SOI layer, forming a monolithic arrangement. EMI/EMC shielding is provided by forming a metallized outer layer on the surface of an external prism coupler that interfaces with the SOI layer, the metallized layer including transparent apertures to allow an optical signal to be coupled into and out of the SOI layer. The opposing surface of the prism coupler may also be coated with a metallic material to provide additional shielding. Further, metallic shielding plates may be formed on the SOI structure itself, overlying the locations of EMI-sensitive electronics. All of these metallic layers are ultimately coupled to an external ground plane to isolate the structure and provide the necessary shielding.Type: ApplicationFiled: December 16, 2004Publication date: June 23, 2005Applicant: SiOptical, Inc.Inventors: David Piede, Margaret Ghiron, Prakash Gothoskar, Robert Montgomery, Vipulkumar Patel, Kalpendu Shastri, Soham Pathak, Katherine Yanushefski
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Publication number: 20050123232Abstract: A planar optical isolator is formed within the silicon surface layer of an SOI structure. A forward-directed signal is applied to an input waveguiding section of the isolator and thereafter propagates through a non-reciprocal waveguide coupling region into an output waveguide section. A rearward-directed signal enters via the output waveguide section and is thereafter coupled into the non-reciprocal waveguide structure, where the geometry of the structure functions to couple only a small amount of the reflected signal into the input waveguide section. In one embodiment, the non-reciprocal structure comprises an N-way directional coupler (with one output waveguide, one input waveguide and N-1 isolating waveguides).Type: ApplicationFiled: December 6, 2004Publication date: June 9, 2005Inventors: David Piede, Margaret Ghiron, Prakash Gothoskar, Robert Montgomery, Vipulkumar Patel, Kalpendu Shastri, Soham Pathak, Katherine Yanushefski, Harvey Wagner
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Publication number: 20050110108Abstract: A silicon-based IR photodetector is formed within a silicon-on-insulator (SOI) structure by placing a metallic strip (preferably, a silicide) over a portion of an optical waveguide formed within a planar silicon surface layer (i.e., “planar SOI layer”) of the SOI structure, the planar SOI layer comprising a thickness of less than one micron. Room temperature operation of the photodetector is accomplished as a result of the relatively low dark current associated with the SOI-based structure and the ability to use a relatively small surface area silicide strip to collect the photocurrent. The planar SOI layer may be doped, and the geometry of the silicide strip may be modified, as desired, to achieve improved results over prior art silicon-based photodetectors.Type: ApplicationFiled: November 17, 2004Publication date: May 26, 2005Inventors: Vipulkumar Patel, Margaret Ghiron, Prakash Gothoskar, Robert Montgomery, Soham Pathak, David Piede, Kalpendu Shastri, Katherine Yanushefski
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Patent number: 6897498Abstract: A photodetector for use with relatively thin (i.e., sub-micron) silicon optical waveguides formed in a silicon-on-insulator (SOI) structure comprises a layer of poly-germanium disposed to couple at least a portion of the optical signal propagating along the silicon optical waveguide. Tight confinement of the optical signal within the waveguide structure allows for efficient evanescent coupling into the poly-germanium detector. The silicon optical waveguide may comprise any desired geometry, with the poly-germanium detector formed to either cover a portion of the waveguide, or be butt-coupled to an end portion of the waveguide. When covering a portion of the waveguide, poly-germanium detector may comprise a “wrap-around” geometry to cover the side and top surfaces of the optical waveguide, with electrical contacts formed at opposing ends of the detector.Type: GrantFiled: February 5, 2004Date of Patent: May 24, 2005Assignee: SiOptical, Inc.Inventors: Prakash Gothoskar, Margaret Ghiron, Vipulkumar Patel, Robert Keith Montgomery, Kalpendu Shastri, Soham Pathak, Katherine A. Yanushefski