Patents by Inventor Kambhampati Ramakrishna
Kambhampati Ramakrishna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060220256Abstract: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.Type: ApplicationFiled: January 4, 2006Publication date: October 5, 2006Inventors: Il Shim, Byung Han, Kambhampati Ramakrishna, Seng Chow
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Publication number: 20060220209Abstract: Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package.Type: ApplicationFiled: March 31, 2006Publication date: October 5, 2006Applicant: STATS ChipPAC Ltd.Inventors: Marcos Karnezos, Il Shim, Byung Han, Kambhampati Ramakrishna, Seng Chow
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Publication number: 20060197205Abstract: A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first plurality of upper leads to form a stack of semiconductor packages.Type: ApplicationFiled: March 2, 2005Publication date: September 7, 2006Applicant: STATS CHIPPAC LTD.Inventors: Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
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Patent number: 7091469Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.Type: GrantFiled: May 20, 2004Date of Patent: August 15, 2006Assignee: ST Assembly Test Services Ltd.Inventors: Dean Paul Kossives, Kambhampati Ramakrishna, Edward Lap Zak Law, Diane Sahakian, Theodore G. Tessier, Jamin Ling
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Publication number: 20050258216Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.Type: ApplicationFiled: May 20, 2004Publication date: November 24, 2005Inventors: Dean Kossives, Kambhampati Ramakrishna, Edward Law, Diane Sahakian, Theodore Tessier, Jamin Ling
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Publication number: 20050236702Abstract: A semiconductor package is provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.Type: ApplicationFiled: June 28, 2005Publication date: October 27, 2005Applicant: STATS ChipPAC, Inc.Inventor: Kambhampati Ramakrishna
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Patent number: 6927479Abstract: A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.Type: GrantFiled: June 25, 2003Date of Patent: August 9, 2005Assignee: St Assembly Test Services LTDInventor: Kambhampati Ramakrishna
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Publication number: 20050090050Abstract: A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is mounted on the interposer.Type: ApplicationFiled: November 10, 2004Publication date: April 28, 2005Applicant: ST ASSEMBLY TEST SERVICES LTD.Inventors: Il Shim, Kambhampati Ramakrishna, Seng Chow, Byung Han
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Publication number: 20050046015Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.Type: ApplicationFiled: August 18, 2004Publication date: March 3, 2005Applicant: ST Assembly Test Services Ltd.Inventors: Il Shim, Kambhampati Ramakrishna, Diane Sahakian, Seng Chow, Dario Filoteo, Virgil Ararao
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Publication number: 20050046012Abstract: A method for fabricating a heat spreader is provided. Heat spreaders are formed and surrounded by a frame. The heat spreaders and frame are connected to one another by tie bars, the heat spreaders and tie bars having respective upper surfaces. At least portions of the upper surfaces of the tie bars are thinned to reduce the heights of the tie bars at least on a singulation line thereon. The frame is formed to support the heat spreader upper surfaces in an elevated position with respect thereto.Type: ApplicationFiled: August 18, 2004Publication date: March 3, 2005Applicant: STATS ChipPAC Ltd.Inventors: Kambhampati Ramakrishna, Diane Sahakian, Il Shim
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Patent number: 6861288Abstract: A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.Type: GrantFiled: September 30, 2003Date of Patent: March 1, 2005Assignee: ST Assembly Test Services, Ltd.Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han
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Patent number: 6841858Abstract: A leadframe design (and method of forming the leadframe design), comprising: an inner die pad structure lying in a first plane; and an outer die pad structure supported by outer tie bars and connected to the inner die pad by inner tie bars. The outer die pad structure lying in a second plane spaced apart from the inner die pad structure first plane. An outer package surrounds at least the inner die pad structure and the inner tie bars. The outer die pad structure being supported by the outer tie bars. The outer package having outer walls. Lead fingers extend through the outer package outer walls and include respective inner portions extending into the outer package proximate the inner and outer die pad structures.Type: GrantFiled: September 27, 2002Date of Patent: January 11, 2005Assignee: ST Assembly Test Services PTE Ltd.Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow
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Publication number: 20040262718Abstract: A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.Type: ApplicationFiled: June 25, 2003Publication date: December 30, 2004Applicant: ST ASSEMBLY TEST SERVICES LTD.Inventor: Kambhampati Ramakrishna
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Publication number: 20040145039Abstract: A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.Type: ApplicationFiled: September 30, 2003Publication date: July 29, 2004Applicant: ST ASSEMBLY TEST SERVICES LTD.Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han
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Publication number: 20040061202Abstract: A leadframe design (and method of forming the leadframe design), comprising: an inner die pad structure lying in a first plane; and an outer die pad structure supported by outer tie bars and connected to the inner die pad by inner tie bars. The outer die pad structure lying in a second plane spaced apart from the inner die pad structure first plane. An outer package surrounds at least the inner die pad structure and the inner tie bars. The outer die pad structure being supported by the outer tie bars. The outer package having outer walls. Lead fingers extend through the outer package outer walls and include respective inner portions extending into the outer package proximate the inner and outer die pad structures.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Applicant: St Assembly Test Services Pte LtdInventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow
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Patent number: 6650019Abstract: This invention provides a method for making a semiconductor package with stacked dies that eliminates fracturing of the upper die(s) during the wire bonding process. One embodiment of the method includes the provision of a substrate and pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed toward the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured, the second die is then wire bonded to the substrate, and the dies are then molded over with an encapsulant.Type: GrantFiled: August 20, 2002Date of Patent: November 18, 2003Assignee: Amkor Technology, Inc.Inventors: Thomas P. Glenn, Lee J. Smith, David A. Zoba, Kambhampati Ramakrishna, Vincent DiCaprio
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Patent number: 6627990Abstract: A stacked die design, and a method of forming the same, comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the lower die and/or the substrate; and an upper die thermally connected to the metal interposer. The lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.Type: GrantFiled: February 6, 2003Date of Patent: September 30, 2003Assignee: St. Assembly Test Service Ltd.Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Gaun Chow
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Patent number: 6531784Abstract: A semiconductor package incorporates spacer strips enabling one or more semiconductor dies having central terminal pads to be stacked on top of one another within the package and reliably wire bonded to an associated substrate without shorting of the bonded wires. Each of the spacer strips comprises a flat, elongated strip of an insulative material that mount at edges of a surface of a die such that they straddle the central terminal pads thereon. The die is electrically connected to the substrate by a plurality of fine conductive wires having a first end bonded to one of the central terminal pad on the die, a second end bonded to a terminal pad on the substrate, and an intermediate portion between the first and second ends that passes transversely across the top surface of one of the spacer strips. The spacer strips have spaced pads or grooves on or in their top surfaces that captivate the individual wires and thereby redistribute the wires and prevent them from contacting the die and each other.Type: GrantFiled: June 2, 2000Date of Patent: March 11, 2003Assignee: Amkor Technology, Inc.Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Vincent DiCaprio
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Publication number: 20020195624Abstract: This invention provides a method for making a semiconductor package with stacked dies that eliminates fracturing of the upper die(s) during the wire bonding process. One embodiment of the method includes the provision of a substrate and pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed toward the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured, the second die is then wire bonded to the substrate, and the dies are then molded over with an encapsulant.Type: ApplicationFiled: August 20, 2002Publication date: December 26, 2002Inventors: Thomas P. Glenn, Lee J. Smith, David A. Zoba, Kambhampati Ramakrishna, Vincent DiCaprio
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Patent number: 6472758Abstract: This invention provides a method for making a semiconductor package with stacked dies that eliminates fracturing of the upper die(s) during the wire bonding process. One embodiment of the method includes the provision of a substrate and pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed toward the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured, the second die is then wire bonded to the substrate, and the dies are then molded over with an encapsulant.Type: GrantFiled: July 20, 2000Date of Patent: October 29, 2002Assignee: Amkor Technology, Inc.Inventors: Thomas P. Glenn, Lee J. Smith, David A. Zoba, Kambhampati Ramakrishna, Vincent DiCaprio