Abstract: This application provides a task migration system and method. The system includes a first terminal and a second terminal. The second terminal runs a first application. The first terminal opens a recent task interface after receiving a user operation, where the recent task interface includes an identifier of the second terminal; after receiving a user operation performed on the identifier of the second terminal, displays, in the recent task interface, at least one task card corresponding to an application run by the second terminal in the background; and after receiving a user operation performed on a first task card corresponding to the first application, runs the first application, and displays a first user interface of the first application.

Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.

Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: The systems and methods described can include approaches to calibrate head-mounted displays for improved viewing experiences. Some methods include receiving data of a first target image associated with an undeformed state of a first eyepiece of a head-mounted display device; receiving data of a first captured image associated with deformed state of the first eyepiece of the head-mounted display device; determining a first transformation that maps the first captured image to the image; and applying the first transformation to a subsequent image for viewing on the first eyepiece of the head-mounted display device.

Abstract: The systems and methods described can include approaches to calibrate head-mounted displays for improved viewing experiences. Some methods include receiving data of a first target image associated with an undeformed state of a first eyepiece of a head-mounted display device; receiving data of a first captured image associated with deformed state of the first eyepiece of the head-mounted display device; determining a first transformation that maps the first captured image to the image; and applying the first transformation to a subsequent image for viewing on the first eyepiece of the head-mounted display device.

Abstract: A physiological signal monitoring device is adapted for monitoring a physiological signal of a biofluid, and includes: a biosensor strip that has at least one signal output end adapted for outputting the physiological signal; a strip reciprocating module that includes a strip seat for receiving the biosensor strip, a guide seat mounted to the strip seat, and a rotating plate mounted rotatably to the strip seat for triggering reciprocating movement of the biosensor strip and the guide seat relative to the strip seat; and a contact module that includes an electronic module, and at least one extending piece connected electrically with the at least one signal output end to transmit the physiological signal to the electronic module.

Abstract: Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.

Abstract: A vehicle power adaptor module includes a vehicle-sided connector and an interchangeable socket. The vehicle-sided connector includes a connector body and a first connecting portion. The first connecting portion is connected with the connector body. The connector body is configured to electrically connect with an electric vehicle. The interchangeable socket includes a socket body and a second connecting portion. The second connecting portion is connected with the socket body. The socket body is configured to electrically connect with an electronic equipment. The second connecting portion is configured to detachably connect with the first connecting portion.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

Abstract: In one embodiment, an AR/VR system includes a social-networking application installed on the AR/VR system, which allows a user to access on online social network, including communicating with the user's social connections and interacting with content objects on the online social network. The AR/VR system also includes an AR/VR application, which allows the user to interact with an AR/VR platform by providing user input to the AR/VR application via various modalities. Based on the user input, the AR/VR platform generates responses and sends the generated responses to the AR/VR application, which then presents the responses to the user at the AR/VR system via various modalities.

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.