Patents by Inventor Kang Huang

Kang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11302600
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Chien-Yuan Huang, Chen-Hsiang Lao
  • Publication number: 20220092747
    Abstract: The systems and methods described can include approaches to calibrate head-mounted displays for improved viewing experiences. Some methods include receiving data of a first target image associated with an undeformed state of a first eyepiece of a head-mounted display device; receiving data of a first captured image associated with deformed state of the first eyepiece of the head-mounted display device; determining a first transformation that maps the first captured image to the image; and applying the first transformation to a subsequent image for viewing on the first eyepiece of the head-mounted display device.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: Lionel Ernest Edwin, Samuel A. Miller, Etienne Gregoire Grossmann, Brian Christopher Clark, Michael Robert Johnson, Wenyi Zhao, Nukul Sanjay Shah, Po-Kang Huang
  • Publication number: 20210407963
    Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Lin, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20210407365
    Abstract: Disclosed are techniques for improving the color uniformity of a display of a display device. A plurality of images of the display are captured using an image capture device. The plurality of images are captured in a color space, with each image corresponding to one of a plurality of color channels. A global white balance is performed to the plurality of images to obtain a plurality of normalized images. A local white balance is performed to the plurality of normalized images to obtain a plurality of correction matrices. Performing the local white balance includes defining a set of weighting factors based on a figure of merit and computing a plurality of weighted images based on the plurality of normalized images and the set of weighting factors. The plurality of correction matrices are computed based on the plurality of weighted images.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 30, 2021
    Applicant: Magic Leap, Inc.
    Inventors: Kevin Messer, Miller Harry Schuck, III, Nicholas Ihle Morley, Po-Kang Huang, Nukul Sanjay Shah, Marshall Charles Capps, Robert Blake Taylor
  • Publication number: 20210391679
    Abstract: A vehicle power adaptor module includes a vehicle-sided connector and an interchangeable socket. The vehicle-sided connector includes a connector body and a first connecting portion. The first connecting portion is connected with the connector body. The connector body is configured to electrically connect with an electric vehicle. The interchangeable socket includes a socket body and a second connecting portion. The second connecting portion is connected with the socket body. The socket body is configured to electrically connect with an electronic equipment. The second connecting portion is configured to detachably connect with the first connecting portion.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 16, 2021
    Inventors: Kang HUANG, Jui-Yen CHIN, Ri-Long LO
  • Patent number: 11200646
    Abstract: The systems and methods described can include approaches to calibrate head-mounted displays for improved viewing experiences. Some methods include receiving data of a first target image associated with an undeformed state of a first eyepiece of a head-mounted display device; receiving data of a first captured image associated with deformed state of the first eyepiece of the head-mounted display device; determining a first transformation that maps the first captured image to the image; and applying the first transformation to a subsequent image for viewing on the first eyepiece of the head-mounted display device.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 14, 2021
    Assignee: Magic Leap, Inc.
    Inventors: Lionel Ernest Edwin, Samuel A. Miller, Etienne Gregoire Grossmann, Brian Christopher Clark, Michael Robert Johnson, Wenyi Zhao, Nukul Sanjay Shah, Po-Kang Huang
  • Publication number: 20210366814
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20210327723
    Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.
    Type: Application
    Filed: October 7, 2020
    Publication date: October 21, 2021
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Patent number: 11152312
    Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20210305145
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20210217147
    Abstract: The systems and methods described can include approaches to calibrate head-mounted displays for improved viewing experiences. Some methods include receiving data of a first target image associated with an undeformed state of a first eyepiece of a head-mounted display device; receiving data of a first captured image associated with deformed state of the first eyepiece of the head-mounted display device; determining a first transformation that maps the first captured image to the image; and applying the first transformation to a subsequent image for viewing on the first eyepiece of the head-mounted display device.
    Type: Application
    Filed: December 21, 2020
    Publication date: July 15, 2021
    Inventors: Lionel Ernest Edwin, Samuel A. Miller, Etienne Gregoire Grossmann, Brian Christopher Clark, Michael Robert Johnson, Wenyi Zhao, Nukul Sanjay Shah, Po-Kang Huang
  • Publication number: 20210202389
    Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.
    Type: Application
    Filed: November 6, 2020
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang
  • Publication number: 20210193550
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Chien-Yuan Huang, Chen-Hsiang Lao
  • Publication number: 20200403775
    Abstract: A universal electronic document verification system with blockchain includes a management interface, configured to connect at least a blockchain; a document deposit terminal, configured to generate a private key and a blockchain account corresponding to the private key, configured to make public an identification (ID) account having the blockchain account and an ID information of document deposit terminal corresponding to the blockchain account, and to generate an original document hash value according to a specific hash function and an electronic document, so as to generate an issued document according to the private key and the original document hash value; and a document verification terminal, configured to receive the electronic document and the corresponding blockchain transaction number to generate a to-be-checked document hash value according to the specific hash function and the electronic document and to submit the blockchain transaction number to the management interface.
    Type: Application
    Filed: April 23, 2020
    Publication date: December 24, 2020
    Inventors: Chih-Kang Huang, Chih-Hsiang Hwang
  • Patent number: 10854567
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou, Shin-Puu Jeng, Bruce C. S. Chou
  • Publication number: 20200337304
    Abstract: Rechargeable antimicrobial materials that can provide continuous sanitation of contact surfaces or liquids are provided that are based on functionalized sanitization particles that are either freestanding or coupled to a surface film. The sanitization particles have a carrier particle and one or more antimicrobial agents loaded into, adsorbed onto or bonded to each carrier particle. The antimicrobial agents may also be joined to a polymer or particulates of clay or zeolite that are coupled to the carrier. Sanitization particles may also be coupled directly to a film or through a chemical linker. The particles and films provide methods of enhanced inactivation of antibiotic resistant bacteria, inactivation and dissipation of biofilms, and the reduction or elimination of bacterial pathogens from surfaces, medical devices, on food or in food containers.
    Type: Application
    Filed: May 11, 2020
    Publication date: October 29, 2020
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Nitin Nitin, Kang Huang
  • Publication number: 20200312770
    Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
  • Patent number: D925137
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 13, 2021
    Inventor: Kang Huang
  • Patent number: D929678
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 31, 2021
    Inventor: Kang Huang
  • Patent number: D930286
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 7, 2021
    Inventor: Kang Huang