Abstract: A semiconductor structure includes a capacitor structure at least partially disposed in a trench of an interlayer dielectric layer. The capacitor structure includes first and second electrode layers separated by a dielectric layer. A top surface of the first electrode layer is below a top surface of the second electrode layer and the dielectric layer. A spacer is disposed on the first electrode layer and a contact is disposed in the trench and connected to the second electrode layer and the spacer.

Abstract: A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

Abstract: An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.

Abstract: Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

Abstract: A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.

Abstract: A semiconductor device including a channel region of stacked semiconductor layers arranged in at least one cluster, wherein each cluster includes a pair of the semiconductor sheets with a dielectric material present therebetween. The semiconductor device further includes a gate structure encapsulating the channel region of stacked semiconductor sheets arranged in clusters. Source and drain regions are present on opposing sides of the channel region.

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

Abstract: A semiconductor structure may include a first nanosheet field-effect transistor formed on a first portion of a substrate, a second nanosheet field-effect transistor formed on a second portion of the substrate, and one or more metal contacts. The first field-effect transistor formed on the first portion of a substrate may include a first source drain epitaxy. A top surface of the first source drain epitaxy may be above a top surface of a top-most nanosheet channel layer. The second nanosheet field-effect transistor formed on the second portion of the substrate may include a second source drain epitaxy and a third source drain epitaxy. The second source drain epitaxy may be below the third source drain epitaxy. The third source drain epitaxy may be u-shaped and may be connected to at least one nanosheet channel layer.

Abstract: A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.

Abstract: A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Abstract: A lower set of semiconductor channel layers, an upper set of semiconductor channel layers, a lower dielectric layer adjacent to the lower set of semiconductor channel layers, the lower dielectric layer includes a first polarity stress on the lower set of semiconductor channel layers, and an upper dielectric layer adjacent to the upper set of semiconductor channel layers, the lower dielectric layer includes a second polarity stress on the upper set of semiconductor channel layers with opposite polarity stress of the first polarity stress. Forming a lower stack of nanosheet layers and an upper stack of nanosheet layers, forming a lower dielectric layer adjacent to the lower stack of nanosheet layers, the lower dielectric layer includes a first polarity stress, and forming an upper dielectric layer adjacent to the upper stack of nanosheet layers, the upper dielectric layer includes a second polarity stress with opposite polarity.

Abstract: A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Abstract: A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

Abstract: A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.

Abstract: Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.

Abstract: A semiconductor device including a substrate having a dense array region and an isolation region. The semiconductor device includes plurality of first fin structures of stacked nanosheets is present in the dense array region separated by a single pitch, wherein each fin structure in the first plurality of fin structures has a same first nanosheet height as measured from an upper surface of the substrate in the dense array region. The semiconductor device further includes at least one second fin structure of stacked nanosheets is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one fin structure having a second nano sheet height that is measured from the upper surface of the substrate in the isolation region that is the same as the first nanosheet height.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: A semiconductor structure includes a substrate comprising a semiconductor material, and a fin on the substrate. The fin includes a first portion formed from the semiconductor material and a second portion including a channel region. The first portion has a first thickness and the second portion has a second thickness greater than the first thickness. A spacer is disposed on sides of the first portion of the fin.