Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

Abstract: A phase change memory (PCM) semiconductor device is provided. The PCM semiconductor device includes: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer; a first electrode on a first side of the phase change material stack; and a second electrode on a second side of the phase change material stack, wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.

Abstract: Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.

Abstract: An approach for providing a semiconductor structure for a stacked magnetoresistive random-access memory (MRAM) device that includes a first magnetic tunnel junction on a bottom electrode and at least one second magnetic tunnel junction above the first magnetic tunnel junction. The semiconductor structure includes the first magnetic tunnel junction is a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction of a voltage-controlled magnetic anisotropy (VCMA) MRAM device. The VCMA-MRAM device is composed of a first reference layer, a first tunnel barrier layer, and a first free layer. The semiconductor structure includes the second magnetic tunnel junction that is a spin-transfer torque (STT) magnetic tunnel junction of a STT-MRAM device. The STT-MRAM device is composed of a second reference layer, a second tunnel barrier layer, and a second free layer where the STT magnetic tunnel junction has a smaller cross-sectional area than the VCMA magnetic tunnel junction (MTJ).

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Abstract: A field effect transistor (FET) structure upon a substrate formed by forming a stack of nanosheets upon a semiconductor substrate, the stack including alternating layers of a compound semiconductor material and an elemental semiconductor material, forming a dummy gate structure upon the stack of nanosheets, recessing the stack of nanosheets in alignment with the dummy gate structure, recessing the compound semiconductor layers beyond the edges of the dummy gate, yielding indentations between adjacent semiconductor nanosheets. Further by filling the indentations with a bi-layer dielectric material, epitaxially growing source/drain regions adjacent to the nanosheet stack and bi-layer dielectric material, removing remaining portions of the compound semiconductor nanosheet layers, recessing the bi-layer dielectric material to expose an inner material layer, and forming gate structure layers in contact with first and second dielectric materials of the bi-layer dielectric material.

Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

Abstract: A phase-change memory device with reduced heater size includes a first conductive structure within a first dielectric layer. A heater element is located within a second dielectric layer disposed above the first conductive structure. The heater element includes a third dielectric layer defining a perimeter, a top portion of a heater material layer partially overlapping the perimeter of the third dielectric layer, and a bottom portion of the heater material layer overlapping the perimeter of the third dielectric layer. The bottom portion of the heater material layer is in contact with the first conductive structure. A phase-change material is located above the heater element with a bottom surface of the phase-change material being in contact with the top portion of the heater material layer. The phase-change memory device further includes a second conductive structure located above the phase-change material.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and a dielectric nanosheet as a top layer of the nanosheet stack is provided above a semiconductor substrate. A dummy gate with a gate cap and spacers on the sidewalls straddle over the nanosheet stack. End portions of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer material layer is formed. A source/drain region is formed on the sidewalls of each semiconductor channel material nanosheet. The dummy gate and gate cap are removed. Each sacrificial semiconductor material nanosheet is removed. A functional gate structure is formed that wraps around each suspended semiconductor channel material nanosheet. A self-aligned source/drain contact region is formed.

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Abstract: A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

Abstract: Embodiments of the invention are directed to a field effect transistor (FET) device including a first channel region over a first region of a substrate; a second channel region over a second region of the substrate and adjacent to the first channel region; and a bottom conductive layer over a third region of the substrate and operable to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact. The first region of the substrate, the second region of the substrate, and the third region of the substrate do not overlap. The bottom conductive layer includes a non-uniform height having a first section and a second section. The first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region.

Abstract: A method of manipulating a molecule having a dipole moment is provided. A non-limiting example of the method includes providing an array of electrodes with each respective electrode in electrical communication with a respective interconnect. Each respective electrode is individually addressable through its respective interconnect, and each respective electrode is capable of generating an electromagnetic field when stimulated. The method provides the molecule above the array of electrodes and stimulates one or more electrodes within the array of electrodes to manipulate the molecule.

Abstract: The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.

Abstract: A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: A semiconductor component includes a first metal layer, a second metal layer, and an MRAM cell. The MRAM cell has a height that is equal to a distance between the first metal layer and the second metal layer. The semiconductor component further includes a first via layer, a third metal layer, and a second via layer. The first via layer, the third metal layer, and the second via layer have a combined height that is equal to the MRAM cell height.

Abstract: Nanopore structures are provided. In one aspect, a nanopore structure includes: an oxide shell surrounding a nanopore, wherein openings on both ends of the nanopore have a diameter D1, and a center of the nanopore has a diameter D2, wherein D1>D2. In another aspect, the nanopore structure includes: a first film disposed on a substrate; a second film disposed on the first film; at least one pore extending through the first film and the second film; a dielectric material disposed in the at least one pore; and a nanopore at a center of the dielectric material in the at least one pore, wherein a top opening to the nanopore has a first diameter d1, and a bottom opening to the nanopore has a second diameter d2, wherein d2>d1. Methods of forming the nanopore structures are also provided.