Abstract: A sense amplification circuit includes a sneak current compensating load current supply unit that selectively switches a load current among load currents having different current amounts and supplies the load current to a bit line selected by a column selection circuit. The sense amplification circuit outputs ‘L’ level when a current amount of the load current is more than a reference current amount, and outputs ‘H’ level when the current amount is less than the reference current amount. A control circuit adjusts the current amount to a predetermined current amount that causes the sense amplification circuit to output ‘H’ level. After the adjustment, the control circuit performs control to supply the load current having the predetermined current amount and controls the writing unit to keep the application until the sense amplification circuit outputs ‘L’ level.

Abstract: In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.

Abstract: Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with little variation caused by positions of memory cells in multi-bit simultaneous writing. The variable resistance nonvolatile memory device includes bit lines, word lines, memory cells, a first write circuit (e.g., a write circuit (60-0)), a second write circuit (e.g., a write circuit (60-k?1)), a first selection circuit (e.g., a selection circuit (S0—0)), a second selection circuit (e.g., a selection circuit (S0_k?1)), and a first word line drive circuit (a word line drive circuit (40-1)), wherein the first selection circuit (e.g., an NMOS transistor (TS0—0—0 to TS0—0_m?1) included in the selection circuit) has a greater ON resistance than the second selection circuit (e.g., an NMOS transistor (TS0_k?1—0 to TS0_k?1_m?1) included in the selection circuit) does.

Abstract: Each memory cell is formed at a different one of cross points of bit lines extending in an X direction and formed in a plurality of layers and word lines extending in a Y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively. Each of the even and odd layer bit line selection switch elements has both a bit line selection function and a current limiting function in low resistance writing.

Abstract: In a method for writing into a variable resistance nonvolatile memory device according to one aspect of the present disclosure, a verify write operation of newly applying a voltage pulse for changing a resistance state is performed on a variable resistance element which does not satisfy a determination condition for verifying that the resistance state has been changed despite application of a voltage pulse for changing the resistance state, and the determination condition in the verify write operation is relaxed when an average number of times of verify write operation, having already been performed on all or part of a plurality of variable resistance elements that are targets for write operation, exceeds a predetermined number of times.

Abstract: A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.

Abstract: A writing method of a variable resistance non-volatile memory element comprises determining, in a first determination step, whether or not a resistance state of the variable resistance non-volatile memory element does not switch to a first resistance state and remains in a second resistance state, when a pulse of a second voltage is applied to the variable resistance non-volatile memory element; and when it is determined that the resistance state of the variable resistance non-volatile memory element does not switch to the first resistance state and remains in the second resistance state in the first determination step, applying, in a recovery step, at least once to the variable-resistance non-volatile memory element a recovery voltage pulse set composed of two pulses which are a first recovery voltage pulse which has the same polarity as that of the first voltage and a second recovery voltage pulse which has the same polarity as that of the second voltage, has a greater amplitude than the second voltage, and

Abstract: A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.

Abstract: A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period P1 among the period P1, a period P2, and a period S that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods P1 and P2 and sets the selected word line to a third voltage different from the first voltage in the period S; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods P2 and S; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period S.

Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.

Abstract: A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate, (ii) a variable resistance element having: lower and upper electrodes; and a variable resistance layer whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes, and (iii) a MOS transistor formed on the substrate, wherein the variable resistance layer includes: oxygen-deficient transition metal oxide layers having compositions MOx and MOy (where x<y) and in contact with the electrodes respectively, a diffusion layer region is connected with the lower electrode to form a memory cell, the region serving as a drain upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer.

Abstract: Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which generates an electric signal for setting the reference cells to LR or HR, and a control circuit which controls operations where application of the generated electric signal to one of the reference cells corresponding to a comparison result of the comparator and application of a new electric signal generated by the pulse generation circuit to one of the reference cells corresponding to a new comparison result of the comparator are repeated, and then one of the reference cells corresponding to a final comparison result of the comparator is connected to an output terminal.

Abstract: A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a second resistance state, remaining in a first resistance state, the set of strong recovery-voltage pulses including pulses: (1) a first strong recovery-voltage pulse which has a greater amplitude than a normal second voltage for changing the resistance state to the first resistance state, and has the same polarity as the second voltage; and (2) a second strong recovery-voltage pulse which follows the first strong recovery-voltage pulse and has a longer pulse width than the pulse width of the normal first voltage for changing the resistance state to the second resistance state, and has the same polarity as the first voltage.

Abstract: Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state.

Abstract: Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with little variation caused by positions of memory cells in multi-bit simultaneous writing. The variable resistance nonvolatile memory device includes bit lines, word lines, memory cells, a first write circuit (e.g., a write circuit (60-0)), a second write circuit (e.g., a write circuit (60-k?1)), a first selection circuit (e.g., a selection circuit (S0—0)), a second selection circuit (e.g., a selection circuit (S0—k?1)), and a first word line drive circuit (a word line drive circuit (40-1)), wherein the first selection circuit (e.g., an NMOS transistor (TS0—0—0 to TS0—0—m?1) included in the selection circuit) has a greater ON resistance than the second selection circuit (e.g., an NMOS transistor (TS0—k?1—0 to TS0—k?1—m?1) included in the selection circuit) does.

Abstract: A sense amplification circuit includes a sneak current compensating load current supply unit that selectively switches a load current among load currents having different current amounts and supplies the load current to a bit line selected by a column selection circuit. The sense amplification circuit outputs ‘L’ level when a current amount of the load current is more than a reference current amount, and outputs ‘H’ level when the current amount is less than the reference current amount. A control circuit adjusts the current amount to a predetermined current amount that causes the sense amplification circuit to output ‘H’ level. After the adjustment, the control circuit performs control to supply the load current having the predetermined current amount and controls the writing unit to keep the application until the sense amplification circuit outputs ‘L’ level.

Abstract: A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period P1 among the period P1, a period P2, and a period S that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods P1 and P2 and sets the selected word line to a third voltage different from the first voltage in the period S; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods P2 and S; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period S.

Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The write circuit sets a variable resistance element of another memory cell different from a faulty memory cell and located on at least one of a bit line and a word line that includes the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in a first low resistance state, by applying a second high-resistance write pulse to the other memory cell.