Abstract: Each memory cell is formed at a different one of cross points of bit lines extending in an X direction and formed in a plurality of layers and word lines extending in a Y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively. Each of the even and odd layer bit line selection switch elements has both a bit line selection function and a current limiting function in low resistance writing.

Abstract: A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.

Abstract: A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.

Abstract: The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of sneak current paths formed by memory cells each including a variable resistance element in a second resistance state having a low resistance value except a selected memory cell in a memory cell array.

Abstract: Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.

Abstract: A variable resistance nonvolatile memory device includes a plurality of memory cells in each of which a variable resistance element and a current steering element having two terminals are connected in series. Additionally, a current limit circuit limits a first current flowing in a direction for changing the memory cells to a low resistance state, and a boost circuit increases, when one of the memory cells changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.

Abstract: A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.

Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.

Abstract: A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate, (ii) a variable resistance element having: lower and upper electrodes; and a variable resistance layer whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes, and (iii) a MOS transistor formed on the substrate, wherein the variable resistance layer includes: oxygen-deficient transition metal oxide layers having compositions MOx and MOy (where x<y) and in contact with the electrodes respectively, a diffusion layer region is connected with the lower electrode to form a memory cell, the region serving as a drain upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer.

Abstract: The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

Abstract: A semiconductor device (100) of the present invention has a structure in which an interlayer insulating layer (115) is formed on an uppermost wire (114), contacts (116, 117) penetrate the interlayer insulating layer (115), a lower electrode (118a) of the resistance variable element is formed on the interlayer insulating layer (115) to cover the contact (116), and resistance variable layer (119) is formed on the interlayer insulating layer (115) to cover the lower electrode (118a) and the contact (117). The contact (116) and the lower electrode (118a) serve as a first terminal, while the contact (117) serves as a second terminal.

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOX and MOy (where x<y) and in contact with the electrodes (309a, 309c) respectively, and a diffusion layer region (302b) is connected with the lower electrode (309a) to form a memory cell (300), the region (302b) serving as a drain of the transistor (317) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer (309b).

Abstract: A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.

Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The write circuit sets a variable resistance element of another memory cell different from a faulty memory cell and located on at least one of a bit line and a word line that includes the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in a first low resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.

Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).

Abstract: Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.

Abstract: In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.

Abstract: A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.