Abstract: A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.

Abstract: A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.

Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.

Abstract: A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements (57, 58) switch electrical connection and disconnection between a global bit line (56) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit (92) having parallel-connected P-type current limiting element (91) and N-type current limiting element (90) is provided between the global bit line and the switch elements.

Abstract: A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.

Abstract: A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.

Abstract: A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.

Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not a current resistance value of the variable resistance element (100) is lower than a resistance value in a high resistance state; and a voltage application step (S36) of applying a voltage pulse having a voltage not exceeding a sum of a forming voltage and a forming margin when the determination is made that the current resistance value is not lower than the resistance value in the high resistance state (No at S35). The determination step (S35) and the voltage application step (S36) are repeated to process all memory cells in a memory array (202) (S34 to S37).

Abstract: A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).

Abstract: A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.

Abstract: Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which generates an electric signal for setting the reference cells to LR or HR, and a control circuit which controls operations where application of the generated electric signal to one of the reference cells corresponding to a comparison result of the comparator and application of a new electric signal generated by the pulse generation circuit to one of the reference cells corresponding to a new comparison result of the comparator are repeated, and then one of the reference cells corresponding to a final comparison result of the comparator is connected to an output terminal.

Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.

Abstract: A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.

Abstract: A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value.

Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).

Abstract: To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state.

Abstract: In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.

Abstract: In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.

Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).