Patents by Inventor Kazuto Takao
Kazuto Takao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200220540Abstract: According to one embodiment, a control circuit is connected to an element portion including a first element. The first element is an RC-IGBT. The first element includes a first gate, a first other gate, a first collector, and a first emitter. The control circuit performs a first operation and a second operation. In at least a portion of the first operation, the control circuit causes a first current to flow from the first collector toward the first emitter. In at least a portion of the second operation, the control circuit causes a second current to flow from the first emitter toward the first collector. In the second operation, the control circuit supplies a first pulse to the first gate and supplies a first other pulse to the first other gate. The first pulse has a first start time and a first end time.Type: ApplicationFiled: September 10, 2019Publication date: July 9, 2020Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Tatsunori SAKANO, Kazuto TAKAO
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Publication number: 20200220538Abstract: According to one embodiment, a control circuit is connected to an element portion including a first element. The first element includes a first gate, a first collector, and a first emitter. The control circuit performs a first operation and a second operation. In at least a portion of the first operation, the control circuit causes a first current to flow from the first collector toward the first emitter. In at least a portion of the second operation, the control circuit causes a second current to flow from the first emitter toward the first collector. A first time constant of a switching of the first element in the first operation is different from a second time constant of a switching of the first element in the second operation.Type: ApplicationFiled: September 3, 2019Publication date: July 9, 2020Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tatsunori SAKANO, Kazuto Takao
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Patent number: 10651161Abstract: According to one embodiment, a semiconductor device includes a first transistor being normally-off, a second transistor being normally-on, and a first conductive member. The first transistor includes a first gate, a first source, a first drain, and a first semiconductor member. The first semiconductor member is provided between the first gate and the first drain and between the first source and the first drain. The second transistor includes a second gate, a second source, a second drain, and a second semiconductor member. An orientation from the first semiconductor member toward the first drain is the same as an orientation from the second semiconductor member toward the second gate, toward the second source, and toward the second drain. The first conductive member electrically connects the first drain and the second source.Type: GrantFiled: March 1, 2018Date of Patent: May 12, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Koyama, Kentaro Ikeda, Kazuto Takao
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Patent number: 10505529Abstract: According to an embodiment, a switching device includes: a switching control unit that connects a first resistor between an input terminal for receiving the switching signal and a gate of a switching transistor during a first period that is an anterior half of a turn-off period of the switching transistor, and connects a second resistor between the input terminal and the gate during a second period that is a posterior half of the turn-off period; a calculating unit that calculates a first gate resistance based on a target voltage rising rate and a first operational expression, and that calculates a second gate resistance based on the permissible maximum voltage value and a second operational expression; and a resistance setting unit that sets resistances of the first resistor and the second resistor based on the first gate resistance and the second gate resistance.Type: GrantFiled: February 27, 2019Date of Patent: December 10, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Kazuto Takao
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Patent number: 10312330Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.Type: GrantFiled: February 27, 2018Date of Patent: June 4, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
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Patent number: 10187057Abstract: A semiconductor module of an embodiment includes a first switching device, a first gate drive circuit controlling ON/OFF of the first switching device, a second switching device connected with the first switching device in parallel or in series, a second gate drive circuit controlling ON/OFF of the second switching device, and a control circuit controlling timing of transmitting a gate drive signal from the first gate drive circuit and transmitting a gate drive signal from the second gate drive circuit by synchronizing the first gate drive circuit and the second gate drive circuit.Type: GrantFiled: February 17, 2017Date of Patent: January 22, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Takao, Kentaro Ikeda
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Publication number: 20190018056Abstract: A semiconductor device according to an embodiment includes a first DC power supply may electrically connected to a gate electrode of a device including first and second electrodes and the gate electrode; an AC signal source may connected to the gate electrode; an inductor having one end connected to the first DC power supply and another end may connected to the gate electrode; a diode provided in parallel to the inductor and having an anode may connected to the gate electrode and a cathode connected to the first DC power supply; a capacitor having one end connected to an AC signal source and another end connected to the anode and another end of the inductor; a second DC power supply may connected to the second electrode; and a switching element having one end may connected to the second electrode and another end connected to the second DC power supply.Type: ApplicationFiled: February 22, 2018Publication date: January 17, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Takashi MIYAZAKI, Kentaro Ikeda, Kazuto Takao
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Publication number: 20180366571Abstract: A semiconductor device includes a first semiconductor layer of silicon carbide, a second semiconductor layer of nitride semiconductor, a third semiconductor layer of nitride semiconductor and a drain electrode. The semiconductor device includes a source electrode that has a first projection portion, a conduction electrode that has a second projection portion and a gate electrode. The first semiconductor layer includes a first region, a second region, a third region and a fourth region.Type: ApplicationFiled: March 5, 2018Publication date: December 20, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Masahiro Koyama, Kentaro Ikeda, Kazuto Takao
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Patent number: 10158012Abstract: A semiconductor device includes a first semiconductor layer of silicon carbide, a second semiconductor layer of nitride semiconductor, a third semiconductor layer of nitride semiconductor and a drain electrode. The semiconductor device includes a source electrode that has a first projection portion, a conduction electrode that has a second projection portion and a gate electrode. The first semiconductor layer includes a first region, a second region, a third region and a fourth region.Type: GrantFiled: March 5, 2018Date of Patent: December 18, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Koyama, Kentaro Ikeda, Kazuto Takao
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Patent number: 10079282Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.Type: GrantFiled: August 29, 2014Date of Patent: September 18, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Mariko Suzuki, Tadashi Sakai, Chiharu Ota, Kazuto Takao, Takashi Shinohe
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Publication number: 20180190775Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
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Patent number: 9950898Abstract: A semiconductor device according to an embodiment includes a plurality of circuit units each includes a first electrode, a second electrode, a switching element portion including first and second switching elements electrically connected between the first electrode and the second electrode, and a capacitor portion including a capacitor electrically connected between the first electrode and the second electrode and stacked with the switching element portion. In two of the adjacent circuit units, the switching element portion of one circuit unit and the capacitor portion of the other circuit unit are adjacent to each other, the capacitor portion of the one and the switching element portion of the other are adjacent to each other, the first electrode of the one and the first electrode of the other are adjacent to each other, and the second electrode of the one and the second electrode of the other are adjacent to each other.Type: GrantFiled: March 7, 2016Date of Patent: April 24, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Takao, Ryosuke Iijima, Tatsuo Shimizu, Teruyuki Ohashi
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Patent number: 9941361Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.Type: GrantFiled: February 5, 2015Date of Patent: April 10, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
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Patent number: 9881912Abstract: A semiconductor device according to an embodiment includes a plurality of circuit units, and each of the circuit units includes, a first electrode, a second electrode; a first switching element and a second switching element electrically connected in series between the first electrode and the second electrode, and a third electrode electrically connected between the first switching element and the second switching element. The circuit units are arranged in an annular shape.Type: GrantFiled: March 7, 2016Date of Patent: January 30, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Takao, Shinya Kyogoku
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Publication number: 20180019750Abstract: A semiconductor module of an embodiment includes a first switching device, a first gate drive circuit controlling ON/OFF of the first switching device, a second switching device connected with the first switching device in parallel or in series, a second gate drive circuit controlling ON/OFF of the second switching device, and a control circuit controlling timing of transmitting a gate drive signal from the first gate drive circuit and transmitting a gate drive signal from the second gate drive circuit by synchronizing the first gate drive circuit and the second gate drive circuit.Type: ApplicationFiled: February 17, 2017Publication date: January 18, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Kazuto TAKAO, Kentaro IKEDA
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Publication number: 20170353128Abstract: A semiconductor device according to an embodiment includes: a first transistor having a first electrode, a second electrode, and a first control electrode, the first transistor performing a switching operation; a second transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, the second transistor performing an analog operation; and a third transistor having a fifth electrode electrically connected to the fourth electrode, a sixth electrode, and a third control electrode.Type: ApplicationFiled: February 13, 2017Publication date: December 7, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kentaro IKEDA, Kazuto TAKAO
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Patent number: 9825121Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.Type: GrantFiled: December 16, 2015Date of Patent: November 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Ryosuke Iijima, Keiko Ariyoshi, Tatsuo Shimizu, Kazuto Takao, Takashi Shinohe
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Patent number: 9812411Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode facing the first electrode, an alternating-current electrode, a first switching element provided between the first electrode and the alternating-current electrode, and a second switching element provided between the second electrode and the alternating-current electrode. The first switching element and the second switching element are electrically connected in series between the first electrode and the second electrode, and the alternating-current electrode is electrically connected between the first switching element and the second switching element.Type: GrantFiled: August 12, 2016Date of Patent: November 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Ikeda, Kazuto Takao, Ryosuke Iijima
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Patent number: 9793824Abstract: A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.Type: GrantFiled: July 13, 2015Date of Patent: October 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Takao, Tatsuo Shimizu, Takashi Shinohe
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Patent number: 9716186Abstract: A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.Type: GrantFiled: October 6, 2015Date of Patent: July 25, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Tatsuo Shimizu, Ryosuke Iijima, Teruyuki Ohashi, Kazuto Takao, Takashi Shinohe