Abstract: A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.

Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed on the first insulating film inside the trench; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a channel region formed between the source region and the drain region in the semiconductor substrate, a second insulating film formed on a surface of the semiconductor substrate; and a control gate electrode formed on the channel region and a surface of the second insulating film. The channel region is adjacent to the trench. A storage state of the nonvolatile semiconductor memory is formed by injecting or drawing charge into or from the floating gate electrode when a tunnel current flows through the first insulating film.

Abstract: It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.

Abstract: It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened.

Abstract: An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is discusssed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or “shared” by adjacent ones of the serially coupled memory cell transistors.

Abstract: A data compression apparatus has a characterizing point extracting part 1 which extracts data expressing characterizing points included in a plurality of data showing a result of carrying out simulation, quantized data generating part 2 which generates quantized data obtained by quantizing data except for data expressing characterizing points, and file number converting part 3 which converts the same types of quantized data including in the quantized data, into a relating file number. In the case of compressing data, data except for the characterizing points is compressed. If the same quantized data is included at the same address location in the previously-compressed file, the quantized data is replaced with the file number of previously-compression file, thereby compressing data at high efficiency.

Abstract: It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened.

Abstract: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.

Abstract: An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is disclosed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or “shared” by adjacent ones of the serially coupled memory cell transistors.

Abstract: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.

Abstract: An electronic device includes a substrate, a first chip mounted on the substrate and having a first terminal, a second terminal, an input pad and a semiconductor time switch connected to the first terminal and the second terminal and configured to disconnect the first terminal and the second terminal upon lapse of a prescribed lifetime, the input pad being configured to set the prescribed lifetime, a second chip mounted on the substrate and incorporating an operational device having a third terminal connected to the first terminal and a fourth terminal serving as an input terminal for an external device, a first memory device mounted on the substrate, having a fifth terminal connected to the second terminal and storing information required for operating the operational device, and an encapsulater covering at least the input pad of the first chip.

Abstract: A semiconductor storage device has a first transistor of first conductive type which control data writing, a second transistor of second conductive type which controls data read-out, a third transistor which amplifies a current corresponding to data to be read out, a first semiconductor layer which is disposed in a predetermined direction, in which a gate of the first transistor is formed, a second semiconductor layer which is disposed separately from the first semiconductor layer in the predetermined direction, in which source and drain of the second transistor and source and drain of the third transistor are formed, a write transistor forming region which is disposed in a direction intersecting the first and second semiconductor layers, in which source and drain of the first transistor, a gate of the third transistor and an electric charge storing region storing electric charge in accordance with data to be written are formed, and a read-out transistor gate region which is disposed in a direction intersecti

Abstract: A data compression apparatus has a characterizing point extracting part 1 which extracts data expressing characterizing points included in a plurality of data showing a result of carrying out simulation, quantized data generating part 2 which generates quantized data obtained by quantizing data except for data expressing characterizing points, and file number converting part 3 which converts the same types of quantized data including in the quantized data, into a relating file number. In the case of compressing data, data except for the characterizing points is compressed. If the same quantized data is included at the same address location in the previously-compressed file, the quantized data is replaced with the file number of previously-compression file, thereby compressing data at high efficiency.

Abstract: A data compression apparatus includes a characterizing point extracting part which extracts data expressing characterizing points included in a plurality of data showing a result of carrying out simulation a quantized data generating part which generates quantized data obtained by quantizing data except for data expressing characterizing points, and a file number converting part which converts the same types of quantized data including in the quantized data, into a relating file number. During data compression, data except for the characterizing points is compressed. If the same quantized data is included at the same address location in the previously-compressed file, the quantized data is replaced with the file number of the previous compression file, thereby compressing data at high efficiency.

Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

Abstract: A semiconductor storage device has a first transistor of first conductive type which control data writing, a second transistor of second conductive type which controls data read-out, a third transistor which amplifies a current corresponding to data to be read out, a first semiconductor layer which is disposed in a predetermined direction, in which a gate of the first transistor is formed, a second semiconductor layer which is disposed separately from the first semiconductor layer in the predetermined direction, in which source and drain of the second transistor and source and drain of the third transistor are formed, a write transistor forming region which is disposed in a direction intersecting the first and second semiconductor layers, in which source and drain of the first transistor, a gate of the third transistor and an electric charge storing region storing electric charge in accordance with data to be written are formed, and a read-out transistor gate region which is disposed in a direction intersecti

Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed on the first insulating film inside the trench; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a channel region formed between the source region and the drain region in the semiconductor substrate, a second insulating film formed on a surface of the semiconductor substrate; and a control gate electrode formed on the channel region and a surface of the second insulating film. The channel region is adjacent to the trench. A storage state of the nonvolatile semiconductor memory is formed by injecting or drawing charge into or from the floating gate electrode when a tunnel current flows through the first insulating film.

Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

Abstract: A semiconductor memory includes first to sixth ridges, an insulating layers on the first to sixth ridges, a first gate line above the first to fourth ridges, and a second gate line above the third to sixth ridges, wherein the first and sixth ridges, the insulating layers, and the first and second gate lines implement first and second capacitors, the second and third ridges and the first gate line implement first driver and load transistors, and the fourth and fifth ridges and the second gate lines implement second load and driver transistors.