Patents by Inventor Kazuya Matsuzawa
Kazuya Matsuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070021953Abstract: A device simulation apparatus has a mesh dividing unit, an impurity concentration setting unit, a reference plane setting unit, an impurity profile determination unit, an impurity surface density determination unit configured to determine the impurity surface density on a surface in a predetermined direction, the surface passing through the position of each impurity atom, a folding unit which folds the impurity surface density corresponding to each impurity atom determined by the impurity surface density determination unit, on the reference plane, and an electric property estimating unit configured to estimate electric properties of the semiconductor device structure by using the impurity surface density on the reference plane folded by the folding unit.Type: ApplicationFiled: July 14, 2006Publication date: January 25, 2007Inventors: Shuichi Toriyama, Kazuya Matsuzawa
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Patent number: 7148537Abstract: A semiconductor memory device includes a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, control insulating films formed on both side faces in a gate length direction of the gate electrode, charge storage layers formed on both the side faces via the control insulating films, a tunnel insulating film formed between the charge storage layers and the semiconductor substrate, and source/drain regions between which the gate electrode and the charge storage layers are interposed, and which are formed in a surface of the semiconductor substrate. Preferably, fixed information is stored depending on presence/absence of an impurity diffusion layer formed in a surface portion of the semiconductor substrate directly under the tunnel insulating film, semi-fixed information is stored depending on an amount of charges in the charge storage layers, and charges opposite to the charges are induced in the surface portion.Type: GrantFiled: March 2, 2005Date of Patent: December 12, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kazuya Matsuzawa
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Publication number: 20060244435Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.Type: ApplicationFiled: June 29, 2006Publication date: November 2, 2006Inventors: Hiroshi Watanabe, Kazuya Matsuzawa, Riichiro Shirota
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Publication number: 20060244434Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.Type: ApplicationFiled: June 29, 2006Publication date: November 2, 2006Inventors: Hiroshi Watanabe, Kazuya Matsuzawa, Riichiro Shirota
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Patent number: 7124378Abstract: A material estimation apparatus which estimates physical properties of an object including two materials contacting each other by performing a simulation for the object, comprising: a transition area setting part which sets a virtual transition area to a contact portion between the two materials; and a power calculation unit which calculates consumption power due to a contact resistance of the transition area based on potential difference of the transition area.Type: GrantFiled: February 28, 2003Date of Patent: October 17, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kazuya Matsuzawa
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Publication number: 20060212709Abstract: It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.Type: ApplicationFiled: February 9, 2006Publication date: September 21, 2006Inventors: Atsuhiro Kinoshita, Kazuya Matsuzawa
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Publication number: 20060197111Abstract: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.Type: ApplicationFiled: June 24, 2005Publication date: September 7, 2006Inventor: Kazuya Matsuzawa
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Publication number: 20060152208Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.Type: ApplicationFiled: February 14, 2006Publication date: July 13, 2006Inventors: Hiroshi Watanabe, Kazuya Matsuzawa, Riichiro Shirota
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Patent number: 7075284Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.Type: GrantFiled: July 3, 2003Date of Patent: July 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Kazuya Matsuzawa, Riichiro Shirota
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Patent number: 7057302Abstract: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode.Type: GrantFiled: August 3, 2004Date of Patent: June 6, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Matsuzawa, Ken Uchida, Takahiro Nakauchi
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Publication number: 20060084215Abstract: Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.Type: ApplicationFiled: November 30, 2005Publication date: April 20, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Kazuya Matsuzawa, Daisuke Hagishima
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Patent number: 6992358Abstract: Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.Type: GrantFiled: June 24, 2004Date of Patent: January 31, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Kazuya Matsuzawa, Daisuke Hagishima
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Publication number: 20050230742Abstract: A semiconductor memory device includes a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, control insulating films formed on both side faces in a gate length direction of the gate electrode, charge storage layers formed on both the side faces via the control insulating films, a tunnel insulating film formed between the charge storage layers and the semiconductor substrate, and source/drain regions between which the gate electrode and the charge storage layers are interposed, and which are formed in a surface of the semiconductor substrate. Preferably, fixed information is stored depending on presence/absence of an impurity diffusion layer formed in a surface portion of the semiconductor substrate directly under the tunnel insulating film, semi-fixed information is stored depending on an amount of charges in the charge storage layers, and charges opposite to the charges are induced in the surface portion.Type: ApplicationFiled: March 2, 2005Publication date: October 20, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuya Matsuzawa
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Publication number: 20050226075Abstract: A semiconductor memory includes first to sixth ridges, an insulating layers on the first to sixth ridges, a first gate line above the first to fourth ridges, and a second gate line above the third to sixth ridges, wherein the first and sixth ridges, the insulating layers, and the first and second gate lines implement first and second capacitors, the second and third ridges and the first gate line implement first driver and load transistors, and the fourth and fifth ridges and the second gate lines implement second load and driver transistors.Type: ApplicationFiled: April 5, 2005Publication date: October 13, 2005Inventor: Kazuya Matsuzawa
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Patent number: 6954723Abstract: There is disclosed a method comprising: calculating a band gap narrowing of a semiconductor and an ionization rate of an impurity in an equilibrium state; calculating a movable electric charge density contributing to transportation of an electric charge inside the semiconductor by solving a Poisson equation and a movable electric charge continuous equation based on the calculated ionization rate in the equilibrium state; calculating said band gap narrowing and said ionization rate in a non-equilibrium state, taking presence of a potential into consideration, based on the calculated movable electric charge density; and repeating the calculation of the movable electric charge density by solving the Poisson equation and the movable electric charge continuous equation based on the ionization rate and the band gap narrowing in said non-equilibrium state, and the calculation of said band gap narrowing and said ionization rate based on the calculation result, until the ionization rate and the band gap narrowing in sType: GrantFiled: September 20, 2001Date of Patent: October 11, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Kazuya Matsuzawa
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Publication number: 20050187751Abstract: A method for evaluating a semiconductor integrated circuit, includes executing device simulation to acquire device simulation values, executing circuit simulation to acquire circuit simulation values of the semiconductor integrated circuit by generating a net list using the device simulation values, and repeating device simulation and circuit simulation until differences between the device simulation values and the circuit simulation values of the connection nodes satisfy judgment conditions so as to set conditions of device simulation employing the circuit simulation values.Type: ApplicationFiled: January 31, 2005Publication date: August 25, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuya Matsuzawa
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Publication number: 20050121703Abstract: Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.Type: ApplicationFiled: June 24, 2004Publication date: June 9, 2005Inventors: Katsuhiko Hieda, Kazuya Matsuzawa, Daisuke Hagishima
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Publication number: 20050062071Abstract: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode.Type: ApplicationFiled: August 3, 2004Publication date: March 24, 2005Inventors: Kazuya Matsuzawa, Ken Uchida, Takahiro Nakauchi
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Publication number: 20040061518Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.Type: ApplicationFiled: July 3, 2003Publication date: April 1, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Kazuya Matsuzawa, Riichiro Shirota
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Publication number: 20030163793Abstract: A material estimation apparatus which estimates physical properties of an object including two materials contacting each other by performing a simulation for the object, comprising: a transition area setting part which sets a virtual transition area to a contact portion between the two materials; and a power calculation unit which calculates consumption power due to a contact resistance of the transition area based on potential difference of the transition area.Type: ApplicationFiled: February 28, 2003Publication date: August 28, 2003Applicant: Kabushiki Kaisha ToshibaInventor: Kazuya Matsuzawa