Patents by Inventor Keishi Inoue

Keishi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942787
    Abstract: A solar cell power conversion device is disposed between a solar cell and a distribution system. A storage battery power conversion device is disposed between a storage battery and the distribution system. An effective voltage calculation circuit calculates an effective voltage of an AC voltage in the distribution system. Based on the effective voltage, a second control circuit and a fourth control circuit control active power and reactive power output from a first DC/AC conversion circuit and a second DC/AC conversion circuit, respectively. When a change in the effective voltage is caused by an operation of an SVR provided in the distribution system, the second and fourth control circuits control operations of the first and second DC/AC conversion circuits to suppress a change in the reactive power caused by the change in the effective voltage.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 26, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Sadayuki Inoue, Tomihiro Takano, Keishi Matsuda
  • Publication number: 20240079877
    Abstract: A power conversion device inputs or outputs a power for changing a state quantity of a distribution grid to which a voltage source device is connected, to or from the distribution grid. A grid control unit calculates a power command value of the power conversion device such that a drooping characteristic is provided for compensating for a deviation from a control target of the state quantity obtained from an output of a detector. A frequency characteristic of control computation for calculating a power command value from the deviation in the system control unit is defined such that a first control gain value in a first frequency range including direct current is set corresponding to a slope of the drooping characteristic, and a second control gain value in a second frequency range including higher frequencies than the first frequency range is set to be lower than the first control gain value.
    Type: Application
    Filed: January 29, 2021
    Publication date: March 7, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki ITOGAWA, Sadayuki INOUE, Tomihiro TAKANO, Keishi MATSUDA, Xiaowei DUI
  • Publication number: 20220293662
    Abstract: The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Keishi INOUE, Kenju NISHIKIDO
  • Patent number: 11398518
    Abstract: The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: July 26, 2022
    Assignee: SONY CORPORATION
    Inventors: Keishi Inoue, Kenju Nishikido
  • Publication number: 20220017984
    Abstract: A ferritic stainless steel sheet has a predetermined chemical composition and thickness, and has an area ratio of crystal grains of 45 ?m or more in grain size of 20% or less.
    Type: Application
    Filed: November 27, 2019
    Publication date: January 20, 2022
    Applicant: JFE STEEL CORPORATION
    Inventors: Keishi INOUE, Hidetaka KAWABE, Masataka YOSHINO, Mitsuyuki FUJISAWA
  • Patent number: 11222914
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 11, 2022
    Assignee: SONY CORPORATION
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20210363604
    Abstract: To provide a hot-rolled and annealed ferritic stainless steel sheet having sufficient corrosion resistance and excellent punching workability, a predetermined dimensional accuracy being obtained without cracking when the steel sheet is formed into a thick-walled flange by punching work, and a method for producing the hot-rolled and annealed ferritic stainless steel sheet. The hot-rolled and annealed ferritic stainless steel sheet has a chemical composition containing, on a mass percent basis, C: 0.001% to 0.020%, Si: 0.05% to 1.00%, Mn: 0.05% to 1.00%, P: 0.04% or less, S: 0.01% or less, Al: 0.01% to 0.10%, Cr: 10.0% to 20.0%, Ni: 0.50% to 2.00%, Ti: 0.10% to 0.40%, and N: 0.001% to 0.020%, the balance being Fe and incidental impurities; and has a metal microstructure which is a single ferrite phase microstructure having an average grain size of 5 to 20 ?m.
    Type: Application
    Filed: September 25, 2019
    Publication date: November 25, 2021
    Applicant: JFE Steel Corporation
    Inventors: Masataka Yoshino, Keishi Inoue, Fagang Gao
  • Patent number: 11139331
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: October 5, 2021
    Assignee: SONY CORPORATION
    Inventors: Kan Shimizu, Keishi Inoue
  • Publication number: 20210043674
    Abstract: The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 11, 2021
    Applicant: SONY CORPORATION
    Inventors: Keishi INOUE, Kenju NISHIKIDO
  • Publication number: 20200385835
    Abstract: The present invention provides a hot-rolled and annealed ferritic stainless steel sheet which has sufficient corrosion resistance and in which cracks can be prevented during blanking into a thick flange, and a method for manufacturing the same. A hot-rolled and annealed ferritic stainless steel sheet has a chemical composition containing, in percent by mass, C: 0.001% to 0.020%, Si: 0.05% to 1.00%, Mn: 0.05% to 1.00%, P: 0.04% or less, S: 0.01% or less, Al: 0.001% to 0.100%, Cr: 10.0% to 19.0%, Ni: 0.65% to 1.50%, Ti: 0.10% to 0.40%, and N: 0.001% to 0.020%, with the balance being Fe and unavoidable impurities, and has a threshold stress intensity factor KIC of 35 MPa·m1/2 or more.
    Type: Application
    Filed: April 24, 2018
    Publication date: December 10, 2020
    Applicant: JFE Steel Corporation
    Inventors: Masataka Yoshino, Keishi Inoue, Mitsuyuki Fujisawa
  • Patent number: 10854657
    Abstract: The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: December 1, 2020
    Assignee: Sony Corporation
    Inventors: Keishi Inoue, Kenju Nishikido
  • Publication number: 20200347475
    Abstract: The present invention provides a ferritic stainless steel sheet and a method for manufacturing the same. A ferritic stainless steel sheet has a composition containing C: 0.001 to 0.020%, Si: 0.05 to 0.35%, Mn: 0.05 to 1.00%, P: 0.04% or less, S: 0.01% or less, Al: 0.001 to 0.300%, Cr: 10.0 to 13.0%, Ni: 0.75 to 1.50%, Ti: 0.05 to 0.35%, and N: 0.001 to 0.020%, with the balance being Fe and inevitable impurities, in which ?I [AD] represented by formula (1) below is 65% or more, and a metal structure has an average crystal grain size of 45 ?m or less: ?I [%]=24Ni+12Mn+6Cu?18Si?12Cr?12Mo+188 (1), where Ni, Mn, Cu, Si, Cr, and Mo represent contents of the respective elements (percent by mass), and an element not contained represents 0.
    Type: Application
    Filed: October 16, 2018
    Publication date: November 5, 2020
    Applicant: JFE Steel Corporation
    Inventors: Keishi Inoue, Hidetaka Kawabe, Masataka Yoshino, Mitsuyuki Fujisawa
  • Patent number: 10812746
    Abstract: Provided is a solid-state imaging device including: an effective pixel region of a substrate, effective pixels being arranged in the effective pixel region; an interconnection region around the effective pixel region, electrodes or interconnects being provided in the interconnection region; a peripheral region outside the interconnection region; and a film formed on the substrate. A cross-sectional height of the film in the effective pixel region is smaller than a cross-sectional height of the film in the interconnection region, and a cross-sectional height of the film in the peripheral region and a cross-sectional height of the film in at least a portion of a middle region between the effective pixel region and the interconnection region, the portion being closer to the interconnection region, are between the cross-sectional height of the film in the effective pixel region and the cross-sectional height of the film in the interconnection region.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Sony Corporation
    Inventors: Yoshiaki Masuda, Kazufumi Watanabe, Kyohei Mizuta, Keishi Inoue, Hirohisa Uchida
  • Publication number: 20200168653
    Abstract: The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
    Type: Application
    Filed: January 5, 2017
    Publication date: May 28, 2020
    Applicant: SONY CORPORATION
    Inventors: Keishi INOUE, Kenju NISHIKIDO
  • Publication number: 20200161362
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Kan Shimizu, Keishi Inoue
  • Patent number: 10651229
    Abstract: The present disclosure relates to a solid-state image device, a method for manufacturing the solid-state image device, and an electronic device that are capable of reducing uneven application of a color filter. A color filter and a plurality of connection unit areas are formed on a sensor board. At least one of the connection unit areas is placed a predetermined interval away from the other connection unit areas. The present disclosure can be applied, for example, to a backside illumination CMOS image sensor with a layer structure, a front-side illumination CMOS image sensor with a layer structure, or a CCD image sensor.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: May 12, 2020
    Assignee: SONY CORPORATION
    Inventors: Yoshiaki Masuda, Kyohei Mizuta, Keishi Inoue, Akira Shinozaki
  • Publication number: 20200144322
    Abstract: A bonding pad formed to a desired thickness is arranged close to a surface of an image sensor. An imaging apparatus includes a semiconductor substrate, a wiring layer, and a signal transmission section. On the semiconductor substrate, a photoelectric conversion section for generating an image signal corresponding to emitted light is formed. The wiring section is formed by having an insulation layer and a wiring layer stacked one on top of the other. The signal transmission section is formed between a recessed section formed on a surface different from the light-receiving surface of the semiconductor substrate on the one hand and the wiring section on the other hand, the signal transmission section being arranged partially in the recessed section. The signal transmission section transmits an image signal transmitted by the wiring layer through an opening formed from the light-receiving surface of the semiconductor substrate toward the recessed section.
    Type: Application
    Filed: June 22, 2018
    Publication date: May 7, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keishi INOUE, Eiichiro KANDA
  • Patent number: 10586823
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 10, 2020
    Assignee: SONY CORPORATION
    Inventors: Kan Shimizu, Keishi Inoue
  • Publication number: 20200013818
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicant: SONY CORPORATION
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 10453886
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue