Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Abstract: A solid-state imaging device includes a first substrate including a light-sensing portion configured to perform photoelectric conversion of incident light and a wiring portion provided on a light-incident side; an optically transparent second substrate provided on a wiring portion side of the first substrate at a certain distance; a through-hole provided in the first substrate; a through-via provided in the through-hole; a front-surface-side electrode connected to the through-via and provided on a front surface of the first substrate; a back-surface-side electrode connected to the through-via and provided on a back surface of the first substrate; and a stopper electrode provided on the front-surface-side electrode and filling a space between the front-surface-side electrode and the second substrate.

Abstract: Provides a semiconductor that enables to suppress deformation of the opening portions due to thermal expansion and contraction and to improve production yield and reliability wiring, and a method of fabricating the same. A first conductive layer and a second conductive layer are formed on a substrate. An insulation film is formed on upper surfaces of the first and second conductive layers and has a plurality of first opening portions to expose either the first or second conductive layer and a plurality of second opening portions to expose neither the first nor the second conductive layer. The second opening portions are formed between the first opening portions. A third conductive layer formed on an upper surface of the insulation film and has an electrical connection between the first and second conductive layers through the first opening portions.

Abstract: A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two.

Abstract: A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two.

Abstract: A method of fabricating a dual damascene interconnection is provided. The method begins by forming on a substrate a dielectric layer and forming a via in the dielectric layer. The dielectric layer is partially etched to form a trench, which is connected to the via and in which interconnections will be formed. A barrier layer is formed that overlies the via and the trench. A copper alloy layer is formed that overlies the barrier layer. The interconnections are completed by filling the trench and the via with copper.

Abstract: Disclosed is a semiconductor device which has a wiring structure including a small-width wiring connected to a large-width wiring through a connection hole or holes formed in an inter-layer insulation film and in which reliability of wiring can be enhanced by regulating the number of the connection hole or holes and the location(s) of the connection hole or hole.

Abstract: Provides a semiconductor that enables to suppress deformation of the opening portions due to thermal expansion and contraction and to improve production yield and reliability wiring, and a method of fabricating the same. A first conductive layer and a second conductive layer are formed on a substrate. An insulation film is formed on upper surfaces of the first and second conductive layers and has a plurality of first opening portions to expose either the first or second conductive layer and a plurality of second opening portions to expose neither the first nor the second conductive layer. The second opening portions are formed between the first opening portions. A third conductive layer formed on an upper surface of the insulation film and has an electrical connection between the first and second conductive layers through the first opening portions.

Abstract: Disclosed is a semiconductor device which has a wiring structure including a small-width wiring connected to a large-width wiring through a connection hole or holes formed in an inter-layer insulation film and in which reliability of wiring can be enhanced by regulating the number of the connection hole or holes and the location(s) of the connection hole or hole.

Abstract: An image display system for display image information obtained by accessing an image data base or the like which was stored in an electronic filing device. The system has: an electronic filing device to store a plurality of pieces of information; a plurality of terminal devices; a common image information memory such as a video RAM to store the image information read out of the electronic filing device on the basis of an instruction from at least one of the terminal devices; and a distributor to distribute and transfer the image information stored in the VRAM to any or all of the terminal devices in accordance with an image transfer instruction from such terminal device(s). A ferroelectric liquid crystal or other display panel which can hold the image information for a predetermined time may be used as a display. The display information can be individually effectively accessed from the electronic filing device by each terminal device while commonly using a single VRAM.

Abstract: A two-sided original reading apparatus includes carrying means for carrying an original in a predetermined carrying direction. First reading circuitry reads the image on the first face of the original at a first reading position and generates first analog image signals. Second reading circuitry reads the image from the second face of the original at a second reading position different from the first reading position with respect to the carrying direction, and generates second analog image signals. Converting circuitry converts the first and second analog signals into first and second digital signals, respectively. Delay circuitry is provided for delaying one of the first and second digital image signals with respect to the other by a delay time which corresponds to a deviation between the first and second reading positions.