Patents by Inventor Keishi Inoue

Keishi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180167572
    Abstract: Provided is a solid-state imaging device including: an effective pixel region of a substrate, effective pixels being arranged in the effective pixel region; an interconnection region around the effective pixel region, electrodes or interconnects being provided in the interconnection region; a peripheral region outside the interconnection region; and a film formed on the substrate. A cross-sectional height of the film in the effective pixel region is smaller than a cross-sectional height of the film in the interconnection region, and a cross-sectional height of the film in the peripheral region and a cross-sectional height of the film in at least a portion of a middle region between the effective pixel region and the interconnection region, the portion being closer to the interconnection region, are between the cross-sectional height of the film in the effective pixel region and the cross-sectional height of the film in the interconnection region.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 14, 2018
    Inventors: YOSHIAKI MASUDA, KAZUFUMI WATANABE, KYOHEI MIZUTA, KEISHI INOUE, HIROHISA UCHIDA
  • Publication number: 20180158859
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: January 19, 2018
    Publication date: June 7, 2018
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20180130842
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Inventors: Kan Shimizu, Keishi Inoue
  • Patent number: 9912890
    Abstract: Provided is a solid-state imaging device including: an effective pixel region of a substrate, effective pixels being arranged in the effective pixel region; an interconnection region around the effective pixel region, electrodes or interconnects being provided in the interconnection region; a peripheral region outside the interconnection region; and a film formed on the substrate. A cross-sectional height of the film in the effective pixel region is smaller than a cross-sectional height of the film in the interconnection region, and a cross-sectional height of the film in the peripheral region and a cross-sectional height of the film in at least a portion of a middle region between the effective pixel region and the interconnection region, the portion being closer to the interconnection region, are between the cross-sectional height of the film in the effective pixel region and the cross-sectional height of the film in the interconnection region.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 6, 2018
    Assignee: SONY CORPORATION
    Inventors: Yoshiaki Masuda, Kazufumi Watanabe, Kyohei Mizuta, Keishi Inoue, Hirohisa Uchida
  • Patent number: 9905602
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 27, 2018
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 9865639
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 9, 2018
    Assignee: Sony Corporation
    Inventors: Kan Shimizu, Keishi Inoue
  • Publication number: 20170077169
    Abstract: The present disclosure relates to a solid-state image device, a method for manufacturing the solid-state image device, and an electronic device that are capable of reducing uneven application of a color filter. A color filter and a plurality of connection unit areas are formed on a sensor board. At least one of the connection unit areas is placed a predetermined interval away from the other connection unit areas. The present disclosure can be applied, for example, to a backside illumination CMOS image sensor with a layer structure, a front-side illumination CMOS image sensor with a layer structure, or a CCD image sensor.
    Type: Application
    Filed: February 24, 2015
    Publication date: March 16, 2017
    Applicant: SONY CORPORATION
    Inventors: Yoshiaki MASUDA, Kyohei MIZUTA, Keishi INOUE, Akira SHINOZAKI
  • Publication number: 20170047369
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 9508772
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 29, 2016
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20160301885
    Abstract: Provided is a solid-state imaging device including: an effective pixel region of a substrate, effective pixels being arranged in the effective pixel region; an interconnection region around the effective pixel region, electrodes or interconnects being provided in the interconnection region; a peripheral region outside the interconnection region; and a film formed on the substrate. A cross-sectional height of the film in the effective pixel region is smaller than a cross-sectional height of the film in the interconnection region, and a cross-sectional height of the film in the peripheral region and a cross-sectional height of the film in at least a portion of a middle region between the effective pixel region and the interconnection region, the portion being closer to the interconnection region, are between the cross-sectional height of the film in the effective pixel region and the cross-sectional height of the film in the interconnection region.
    Type: Application
    Filed: March 12, 2014
    Publication date: October 13, 2016
    Inventors: Yoshiaki MASUDA, Kazufumi WATANABE, Kyohei MIZUTA, Keishi INOUE, Hirohisa UCHIDA
  • Publication number: 20160181303
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Inventors: Kan Shimizu, Keishi Inoue
  • Publication number: 20160133665
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 12, 2016
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 9287311
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 15, 2016
    Assignee: SONY CORPORATION
    Inventors: Kan Shimizu, Keishi Inoue
  • Patent number: 9276033
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 1, 2016
    Assignee: SONY CORPORATION
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20150108599
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: December 31, 2014
    Publication date: April 23, 2015
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 8946898
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20130320475
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 5, 2013
    Applicant: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 8541878
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 24, 2013
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20130082341
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Application
    Filed: August 16, 2012
    Publication date: April 4, 2013
    Applicant: SONY CORPORATION
    Inventors: Kan SHIMIZU, Keishi INOUE
  • Patent number: 8410569
    Abstract: A solid-state imaging device includes a first substrate including a light-sensing portion configured to perform photoelectric conversion of incident light and a wiring portion provided on a light-incident side; an optically transparent second substrate provided on a wiring portion side of the first substrate at a certain distance; a through-hole provided in the first substrate; a through-via provided in the through-hole; a front-surface-side electrode connected to the through-via and provided on a front surface of the first substrate; a back-surface-side electrode connected to the through-via and provided on a back surface of the first substrate; and a stopper electrode provided on the front-surface-side electrode and filling a space between the front-surface-side electrode and the second substrate.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 2, 2013
    Assignee: Sony Corporation
    Inventors: Ikuo Yoshihara, Masaya Nagata, Naoto Sasaki, Taku Umebayashi, Hiroshi Takahashi, Yoichi Otsuka, Isaya Kitamura, Tokihisa Kaneguchi, Keishi Inoue, Toshihiko Hayashi, Hiroyasu Matsugai, Mayoshi Aonuma, Hiroshi Yoshioka