Patents by Inventor Keitaro Uehara
Keitaro Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120198446Abstract: A hypervisor records error device information in a virtual PCI bridge, and makes error information in a device consistent with error information in a PCI bridge. A computer system includes a CPU, memory, and physical device PCI tree. In the memory, virtual machines capable of mutually independently acting, and a hypervisor that manages the virtual machines are existent. The physical device PCI tree includes physical bridges and devices. The physical bridge has a register in which information specifying the device is recorded. The virtual machine includes a virtual CPU, virtual memory, and virtual device PCI tree. The virtual device tree includes virtual bridges and virtual devices. The virtual bridge has a virtual memory space in which information specifying the virtual device in which an error has occurred is recorded. The hypervisor includes an interrupt handling program that is a virtual bridge modification program which modifies information in the virtual bridge.Type: ApplicationFiled: January 18, 2012Publication date: August 2, 2012Applicant: Hitachi, Ltd.Inventors: Yuta SAWA, Naoya HATTORI, Keitaro UEHARA
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Patent number: 8214559Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.Type: GrantFiled: August 4, 2011Date of Patent: July 3, 2012Assignee: Hitachi, Ltd.Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
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Publication number: 20120117226Abstract: There is provided a monitoring system capable of representing relationships of computer resources that virtual servers use in a tree structure and aggregating the performance statistics of the virtual resources sharing physical resources. The monitoring system has: a virtualization module that makes virtual computers operate; and a monitoring module for monitoring the physical computers and components of the virtual computers.Type: ApplicationFiled: November 2, 2011Publication date: May 10, 2012Applicant: HITACHI, LTD.Inventors: Tsuyoshi TANAKA, Keitaro UEHARA, Shinichi KAWAMOTO
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Patent number: 8078764Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.Type: GrantFiled: August 20, 2008Date of Patent: December 13, 2011Assignee: Hitachi, Ltd.Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Keitaro Uehara, Yuji Tsushima
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Publication number: 20110289502Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.Type: ApplicationFiled: August 4, 2011Publication date: November 24, 2011Applicant: HITACHI, LTD.Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
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Patent number: 8046520Abstract: A resource management module of a management server for controlling a multi-root I/O manager connected to a PCI switch for connecting a plurality of I/O devices and a plurality of computers with each other includes: failure handling content information indicating, for each computer sharing a multi-root I/O device, a content of a failure handling at an occurrence of a failure in the multi-root I/O device; and failure handling availability status information indicating whether a hardware reset of the multi-root I/O device is possible and updates, upon reception of a notification of the occurrence of the failure in the multi-root I/O device, the failure handling availability status information, and instructs, based on the failure handling availability status information, the multi-root I/O manager to restrain or cancel the hardware reset of the multi-root I/O device.Type: GrantFiled: December 11, 2009Date of Patent: October 25, 2011Assignee: Hitachi, Ltd.Inventors: Takashige Baba, Keitaro Uehara, Yuji Tsushima
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Publication number: 20110238817Abstract: A failure factor can be promptly carved up by effectively prioritizing the ports to which MEPs are assigned in a condition where the maximum number of MEPs is limited. A network monitoring server monitors a network having plural switch devices. The plural switch devices each have a communication confirmation function using transmission and reception of a monitoring frame between ports. An upper limit is set to the number of ports to which maintenance end points (MEPs) are assignable among the respective ports of the plural switch devices. The network monitoring server calculates, for each of the plural switch devices, a monitoring priority corresponding to the probability of failures of a device connected to a network path including the port or the port, and generates data for displaying the calculated monitoring priority of each port in association with each port.Type: ApplicationFiled: December 29, 2010Publication date: September 29, 2011Applicant: Hitachi, Ltd.Inventors: Hideki OKITA, Masahiro Yoshizawa, Keitaro Uehara
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Patent number: 8010719Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.Type: GrantFiled: June 29, 2007Date of Patent: August 30, 2011Assignee: Hitachi, Ltd.Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
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Patent number: 7975076Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.Type: GrantFiled: September 8, 2010Date of Patent: July 5, 2011Assignee: Hitachi, Ltd.Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
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Patent number: 7925817Abstract: A computer system includes I/O devices coupled to PCI switches coupled via interfaces of a plurality of servers, and a management block for managing configurations of the PCI switches. The management block is configured to: set, to the PCI switch, a first access path including a virtual bridge coupling the interface of an active server and a virtual switch, and a virtual bridge coupling the I/O device and the virtual switch; set, to the PCI switch, a second access path including a virtual bridge coupling the interface of standby server of the plurality of servers and a virtual switch, and a virtual bridge coupling the I/O device used by the active server and the virtual switch; disable mapping of the second access path between the I/O device and the virtual bridge; and instruct the standby server to make access to the I/O device.Type: GrantFiled: April 13, 2009Date of Patent: April 12, 2011Assignee: Hitachi, Ltd.Inventors: Keitaro Uehara, Yuji Tsushima, Takashige Baba
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Patent number: 7890669Abstract: Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.Type: GrantFiled: November 20, 2006Date of Patent: February 15, 2011Assignee: Hitachi, Ltd.Inventors: Keitaro Uehara, Yuji Tsushima, Toshiomi Moriki, Yoshiko Yasuda
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Publication number: 20110004706Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.Type: ApplicationFiled: September 8, 2010Publication date: January 6, 2011Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
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Publication number: 20100312943Abstract: It is provided a computer system comprising a plurality of computers; a PCI switch; and a plurality of I/O devices connected to the PCI switch, wherein the communication path includes a virtual switch and virtual bridges, and the PCI switch comprises a communication path generating module for setting the virtual switches and the virtual bridges, a virtual switch group management module for creating a virtual switch group including the at least one of the virtual switches, and setting an enabled flag to one of the virtual switches included in the virtual switch group, and a port management module for managing relation between each of the generated communication paths and the plurality of ports included in the each of the generated communication paths.Type: ApplicationFiled: May 28, 2010Publication date: December 9, 2010Applicant: HITACHI, LTD.Inventors: Keitaro UEHARA, Takashige BABA, Yuji TSUSHIMA
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Patent number: 7797466Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.Type: GrantFiled: April 29, 2009Date of Patent: September 14, 2010Assignee: Hitachi, Ltd.Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
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Publication number: 20100211717Abstract: It is provided a computer system including computers, PCI switches each having first and second ports, a switch management module and a power control module. The switch management module includes an identifying module for identifying a first port coupled to the computer to be booted up, and notifying the PCI switch of the first port, an instruction module for instructing the power control module to boot up the computer, and an allocation management module for managing allocation of one of the I/O device to the computer and notifying the one of the PCI switches of the allocation after the computer is booted up. The PCI switches includes a preventing control module for preventing the computer from detecting a configuration of the first port, and a virtual switch generating module for generating a virtual switch that couples the first port and the second port based on the notification.Type: ApplicationFiled: February 19, 2010Publication date: August 19, 2010Inventors: Keitaro Uehara, Takashige Baba, Yuji Tsushima
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Publication number: 20100153615Abstract: A resource management module of a management server for controlling a multi-root I/O manager connected to a PCI switch for connecting a plurality of I/O devices and a plurality of computers with each other includes: failure handling content information indicating, for each computer sharing a multi-root I/O device, a content of a failure handling at an occurrence of a failure in the multi-root I/O device; and failure handling availability status information indicating whether a hardware reset of the multi-root I/O device is possible and updates, upon reception of a notification of the occurrence of the failure in the multi-root I/O device, the failure handling availability status information, and instructs, based on the failure handling availability status information, the multi-root I/O manager to restrain or cancel the hardware reset of the multi-root I/O device.Type: ApplicationFiled: December 11, 2009Publication date: June 17, 2010Applicant: HITACHI, LTD.Inventors: Takashige BABA, Keitaro UEHARA, Yuji TSUSHIMA
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Patent number: 7725632Abstract: Disclosed herewith is a composite type computer system that can assure that a PCI tree to be allocated to a computer is configured completely before the computer is powered. The composite type computer system includes a PCI switch that connects plural computers through PCI interfaces; plural PCI devices connected to the PCI switch; a system controller that controls the computers; and a PCI manager that controls allocation of the PCI devices to the computers.Type: GrantFiled: August 5, 2008Date of Patent: May 25, 2010Assignee: Hitachi, Ltd.Inventors: Takashige Baba, Jun Okitsu, Yuji Tsushima, Nobuyuki Muranaka, Keitaro Uehara
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Publication number: 20100082874Abstract: In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information.Type: ApplicationFiled: August 24, 2009Publication date: April 1, 2010Inventors: Takashige BABA, Toshiomi Moriki, Keitaro Uehara
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Publication number: 20100036995Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.Type: ApplicationFiled: June 18, 2009Publication date: February 11, 2010Applicant: HITACHI, LTD.Inventors: Keishi Nakayama, Keitaro Uehara, Takashi Aoyagi, Shinichiro Toya
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Patent number: 7613885Abstract: In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.Type: GrantFiled: August 31, 2006Date of Patent: November 3, 2009Assignee: Hitachi, Ltd.Inventors: Keitaro Uehara, Jun Okitsu, Yoshiki Murakami