Patents by Inventor Keitaro Uehara

Keitaro Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090265501
    Abstract: Provided is a computer system including I/O devices coupled to PCI switches coupled via interfaces of a plurality of servers, and a management block for managing configurations of the PCI switches. The management block is configured to: set, to the PCI switch, a first access path including a virtual bridge coupling the interface of a first server and a virtual switch, and a virtual bridge coupling the I/O device and the virtual switch; set, to the PCI switch, a second access path including a virtual bridge coupling the interface of a second server of the plurality of servers and a virtual switch, and a virtual bridge coupling the I/O device used by the first server and the virtual switch; disable mapping of the second access path between the I/O device and the virtual bridge; and instruct the second server to make access to the I/O device.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 22, 2009
    Applicant: HITACHI, LTD.
    Inventors: Keitaro Uehara, Yuji Tsushima, Takashige Baba
  • Publication number: 20090216913
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 27, 2009
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20090198862
    Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
    Type: Application
    Filed: August 20, 2008
    Publication date: August 6, 2009
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20090187694
    Abstract: Disclosed herewith is a composite type computer system that can assure that a PCI tree to be allocated to a computer is configured completely before the computer is powered. The composite type computer system includes a PCI switch that connects plural computers through PCI interfaces; plural PCI devices connected to the PCI switch; a system controller that controls the computers; and a PCI manager that controls allocation of the PCI devices to the computers.
    Type: Application
    Filed: August 5, 2008
    Publication date: July 23, 2009
    Inventors: Takashige Baba, Jun Okitsu, Yuji Tsushima, Nobuyuki Muranaka, Keitaro Uehara
  • Publication number: 20090150896
    Abstract: Provided is a method of controlling a virtual computer system in which a physical computer includes a plurality of physical CPUs that is switchable between a sleep state and a normal state, and a virtualization control unit divides the physical computer into a plurality of logical partitions to run a guest OS in each of the logical partitions and controls allocation of resources of the physical computer to the logical partitions, causes the virtualization control unit to: receive an operation instruction for operating the logical partitions; and if the operation instruction is for deleting a virtual CPU from one of the logical partitions, delete this virtual CPU from a table for managing virtual CPU-physical CPU allocation and put, if the deleting leaves no virtual CPUs allocated to one of the physical CPUs that has been allocated the deleted virtual CPU, this one of the physical CPUs into the sleep state.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 11, 2009
    Inventors: Yuji TSUSHIMA, Keitaro UEHARA, Toshiomi MORIKI, Naoya HATTORI
  • Publication number: 20090138887
    Abstract: In order to provide an interface of acquiring physical position information of an I/O device on a virtual machine monitor having an exclusive allocation function of the I/O device and optimize allocation of a resource to a virtual server by using the acquired physical position information, a virtual machine monitor includes an interface of allocating a resource in accordance with a given policy (a parameter of determining to which a priority is given in distributing resources) for an I/O device, a CPU NO., and a memory amount request to guest OS. Further, the virtual machine monitor includes an interface of pertinently converting physical position information of the resource allocated by the virtual machine monitor to notice to guest OS.
    Type: Application
    Filed: August 5, 2008
    Publication date: May 28, 2009
    Inventors: Keitaro Uehara, Yuji Tsushima
  • Patent number: 7539788
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: May 26, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20080172499
    Abstract: The present invention provides a machine system that enables the arbitration of IO accesses and band control based on the priority of virtual servers while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system including a CPU, a memory, and an IO interface includes a hypervisor that generates plural virtual servers, and an IO controller that controls the IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.
    Type: Application
    Filed: June 29, 2007
    Publication date: July 17, 2008
    Inventors: Toshiomi MORIKI, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20080162734
    Abstract: When the entire system is split into plural partitions on chipsets connecting plural processors, IO hubs, and memory controllers, and an OS is operating on each of the partitions, the present invention prevents a failure in a partition from propagating to other partitions. Based on address information or issuer information included in a packet inputted to a chipset, a partition from which the packet was issued is identified, and an identified partition identifier is added to the packet. Based on the added partition identifier, a partition initializing part selectively deletes the packet issued from the partition in which a failure occurred, thereby preventing the influence of the failure in the failure-causing partition from propagating to other partitions.
    Type: Application
    Filed: June 27, 2007
    Publication date: July 3, 2008
    Inventors: Keitaro UEHARA, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 7313637
    Abstract: Disclosed herein is a computer system provided with a mechanism for connecting a single port disk to an active server and the disk to a standby server when in a fail-over processing. An “add_pci” command issued from a clustering program is used to let a control program change the allocation of a PCI slot while an interruption signal issued to a standby server permits an ACPI processing routine to hot-add a PCI card that includes the disk unit on the subject guest OS.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 25, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Tanaka, Keitaro Uehara, Yuji Tsushima, Naoki Hamanaka, Daisuke Yoshida, Yoshinori Wakai
  • Publication number: 20070156972
    Abstract: In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.
    Type: Application
    Filed: August 31, 2006
    Publication date: July 5, 2007
    Inventors: Keitaro Uehara, Jun Okitsu, Yoshiki Murakami
  • Publication number: 20070143395
    Abstract: Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.
    Type: Application
    Filed: November 20, 2006
    Publication date: June 21, 2007
    Inventors: Keitaro UEHARA, Yuji Tsushima, Toshiomi Moriki, Yoshiko Yasuda
  • Publication number: 20060236040
    Abstract: A case occurs in which a preceding transaction to be retried cannot be retried as a result of snooping. If the snoop result is waited for so that a retry decision may be made after the result of snoop has been obtained, latency is prolonged to urge the pipeline to have a variable length, thus complicating the logic. A transaction determined to be retried in the phase of issue of a request is discriminated from a transaction in course of issue and when a transaction representing a starvation protection object sequentially competes twice with the transaction in course of retry decision, the transaction of starvation protection object is issued to thereby eliminate starvation.
    Type: Application
    Filed: April 18, 2006
    Publication date: October 19, 2006
    Inventors: Keitaro Uehara, Jun Okitsu, Yoshiki Murakami, Takashi Miyata
  • Publication number: 20060224931
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Application
    Filed: June 6, 2006
    Publication date: October 5, 2006
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Patent number: 7080291
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: July 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20050097384
    Abstract: The present invention makes coordination of I/O access operations of operating systems independently running in logical partitions. In a data processing system comprising processors, a main memory, I/O slots, and a node controller, wherein the processors, the main memory, and the I/O slots are interconnected via the node controller and divided into a plurality of partitions in which individual operating systems are run simultaneously, the node controller includes a logical partition arbitration unit which stores information as to whether each logical partition is using an I/O slot and controls access from each logical partition to an I/O slot by referring to the information thus stored.
    Type: Application
    Filed: July 12, 2004
    Publication date: May 5, 2005
    Inventors: Keitaro Uehara, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 6874053
    Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara
  • Publication number: 20050010667
    Abstract: A sever includes an SVP 206 which is a control device capable of executing processing independent of a CPU, and an interrupt 314 is periodically applied to the CPU. An SVP device driver 303, being triggered by the interrupt 314, acquires an amount of server resources used, such as CPU operating time and memory capacity, and user information used by using an API provided by an OS, and delivers such information to an SVP 206. The SVP 206 transmits resource information thus delivered to an accounting server via an NIC 211. The accounting server accounts an amount of server resource used on a user basis and bills the users according to the quantity of server resource used. With such arrangement, it is possible to accurately grasp the usage status of server resource regardless of server loading, and further, it is possible to execute accounting of server resources and billing based on such accounting regardless of types of OS or CPU.
    Type: Application
    Filed: January 6, 2004
    Publication date: January 13, 2005
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima, Tsuyoshi Tanaka
  • Publication number: 20040210646
    Abstract: The present invention relates to system construction, and operations management, provided by a plurality of servers in an information processing system, and more particularly to a technology for reducing the burden on a system administrator for system construction and operations management.
    Type: Application
    Filed: January 16, 2004
    Publication date: October 21, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yuji Sushima, Tsuyoshi Tanaka, Keitaro Uehara, Naoki Hamanaka
  • Publication number: 20040187106
    Abstract: Disclosed herein is a computer system provided with a mechanism for connecting a single port disk to an active server and the disk to a standby server when in a fail-over processing. An “add_pci” command issued from a clustering program is used to let a control program change the allocation of a PCI slot while an interruption signal issued to a standby server permits an ACPI processing routine to hot-add a PCI card that includes the disk unit on the subject guest OS.
    Type: Application
    Filed: December 5, 2003
    Publication date: September 23, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Tsuyoshi Tanaka, Keitaro Uehara, Yuji Tsushima, Naoki Hamanaka, Daisuke Yoshida, Yoshinori Wakai