Abstract: In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.

Abstract: In a computer system comprising a plurality of computers interconnected by a network, the following steps are implemented: checking the booting of the individual computers when their power is turned on, checking the available memory space and I/O volumes on the individual computers, and determining a schedule of interleaving the memory and the I/O components. Thereby, the invention provides a multiprocessor system operating with shared memory units in a multiplex manner. In a computer system comprising elemental servers (each functioning as a single server unit and has an SSP) and a network interconnecting the servers. The SSP in conjunction with a chip set provides means for communication through control packets transmitted over the network. The SSP controls the components of the elemental server including the power supply unit.

Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

Abstract: An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs.

Abstract: In a computer system comprising a plurality of computers interconnected by a network, the following steps are implemented: checking the booting of the individual computers when their power is turned on, checking the available memory space and I/O volumes on the individual computers, and determining a schedule of interleaving the memory and the I/O components. Thereby, the invention provides a multiprocessor system operating with shared memory units in a multiplex manner. In a computer system comprising elemental servers (each functioning as a single server unit and has an SSP) and a network interconnecting the servers. The SSP in conjunction with a chip set provides means for communication through control packets transmitted over the network. The SSP controls the components of the elemental server including the power supply unit.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: In a computer having a plurality of processors or in a computer cluster system, processing performance is improved by measuring operation characteristics of a process, and by performing process scheduling on the basis of actual measurements of the process operation characteristics.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: A processor system and method whereby a successive transaction which depends upon a preceding transaction is sent without waiting for the completion of the preceding transaction issued from an I/O bus to a memory. A source side I/O unit consecutively issues transactions from an I/O bus. A reply side node controller unit or transfer unit has an I/O flag register for recording a reply-requested or reply-pending preceding transaction to assure transactions from the same I/O bus are sequentially completed according to certain bus protocols. Consequently, the reply side node controller unit or transfer unit retries or suspends the reply to the successive transaction, when retry of a preceding transaction is requested or its reply is suspended. Various internal registers and counters may be used.

Abstract: A multiprocessor system that performs processing of transactions issued consecutively by Posted Write with a device on an I/O bus as a transaction source or target. If one of a series of transactions with a device on some I/O bus of a plurality of I/O buses in the system as source is retried at a target node, the subsequent transactions from that I/O bus also are retried, and the sending unit of the source node reissues these transactions. At that time, a header flag is added to the first of a series of reissued transactions. At the transaction processing unit of the target node, if processing is impossible, a retry flag is set with the bit corresponding to the I/O bus of the issuing source in the retry flag register and a retry is returned to the source, and henceforth retries are returned also when receiving subsequent transactions with the same I/O bus as issuing source. When the resent transaction added the header flag is received, whether or not processing is possible is judged again.

Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.