Patents by Inventor Kenji Matsuo

Kenji Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5263370
    Abstract: A liquidometer composed of a siphon for emitting a sample liquid stored in a reservoir and a liquid level sensor for sensing the level of the sample remained in the reservoir. The siphon further includes a pair of sensors for counting the number of emission thereof, while the liquid level sensor includes two rows of resistive film with a plurality of sensing elements embedded therein. Outside the liquidometer, there are provided a counter connected to the emission sensor, a level calculator connected to the liquid level sensor, and a calculator coupled to both. A gross amount of the sample liquid having been measured for a period of hours is obtained by adding together a count signal from the counter which represents the quantity of the sample liquid fully stored in the reservoir and a signal from the level counter which represents the liquid level of the remaining sample liquid.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: November 23, 1993
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Michihiro Murata, Akira Kumada, Kenji Matsuo, Shigeo Yamazaki
  • Patent number: 5250630
    Abstract: A heat resistant pneumatic tire whose tread is composed of a rubber composition comprising, as a main rubber component, a modified, conjugated diene based polymer prepared by adding an .alpha., .beta.-unsaturated carboxylic acid represented by the following general formula: ##STR1## wherein R.sub.1, R.sub.2 and R.sub.3 independently represent hydrogen atom, halogen atom, or an alkyl, alkenyl or allyl group having at most 5 carbon atoms, or a substituted alkyl, alkenyl or allyl group,to a conjugated diene based polymer in an amount within the range between 0.1% and 5.0% based on the weight of the conjugated diene based polymer. This tire is suitable for continuous running at high temperatures and maintains a good road-surface-grip performance even during such running.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: October 5, 1993
    Assignee: Bridgestone Corporation
    Inventors: Nobumitsu Oshima, Takashi Kitamura, Ryota Fujio, Kenji Matsuo
  • Patent number: 5235218
    Abstract: This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementar
    Type: Grant
    Filed: November 14, 1991
    Date of Patent: August 10, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Matsuo, Shinji Fujii, Yasukazu Noine, Kazuhiko Kasai
  • Patent number: 5226313
    Abstract: A body fluid excretion volume measurement apparatus for medical application. The apparatus stores body fluid excreted from patients in a body fluid storage tank and measures the resistance value with a resistance sensor. The resistance value depends on the shape of the body fluid storage tank, and if the tank is columnar, the resistance value is monotonically increasing with respect to the depth of body fluid. The output of the resistance sensor is processed by a measurement part and electric measurement of the body fluid volume stored in the body fluid storage tank is performed automatically.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: July 13, 1993
    Assignees: Murata Mfg. Co., Ltd., Kobayashi Pharmaceutical Co., Ltd.
    Inventors: Michihiro Murata, Akira Kumada, Kenji Matsuo, Chitaka Ochiai, Shigeo Yamazaki, Masaaki Kimura, Naoyuki Kohriya
  • Patent number: 5200637
    Abstract: A MOS transistor includes a gate electrode layer formed on an insulation layer which is formed on an element formation region defined by a field insulation layer formed on a P-type semiconductor substrate. The gate electrode layer has first and second openings formed therein. Further, N-type impurity diffusion regions acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate which lie under the first and second openings.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: April 6, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Matsuo, Yasukazu Noine, Kazuhiko Kasai
  • Patent number: 5148708
    Abstract: A liquid level sensor for detecting a level of an electrolyte where: a pair of resistance films are formed on an insulating substrate: a plurality of electrodes are intermittently mounted on the resistance films in the longitudinal direction; the resistance films are soaked in the electrolyte in the vertical direction along the longitudinal direction; the liquid surface is detected from the variation of the resistance value of the resistance films caused by the short-circuiting of pairs of the electrodes in the electrolyte. The exposed surface of the resistance film is covered by a moisture-resistance film. The result is that undesirable change of resistance value of the resistance film caused by being moistened can be reliably prevented.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: September 22, 1992
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Michihiro Murata, Akira Kumada, Shigeo Yamazaki, Kenji Matsuo
  • Patent number: 5146120
    Abstract: A low-noise output buffer circuit of this invention comprises a P-channel MOSFET having a source connected to a power source potential, for outputting the power source potential according to a first input signal, an N-channel MOSFET having a source connected to a ground potential, for outputting the ground potential according to a second input signal, a bipolar transistor having a collector connected to the power source potential, an emitter connected to an output terminal and a base connected to the drain of the P-channel MOSFET, and a diode having a cathode connected to the drain of the N-channel MOSFET and an anode connected to the base of the NPN bipolar transistor.
    Type: Grant
    Filed: July 25, 1991
    Date of Patent: September 8, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Kimura, Kenji Matsuo, Ikuo Tsuchiya, Masayo Fukuda
  • Patent number: 5136293
    Abstract: This invention is a D/A converter including a preset current source, first and second differential switches for selectively deriving an output current of the preset current source in response to complementary signals supplied to control electrodes thereof, and an imaginary short circuit for connecting output portions of current paths of the switches to each other. Variation in the voltage at the time of switching operation of the differential switch can be suppressed by use of the imaginary short circuit with the above construction, thus making it possible to enhance the operation speed.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: August 4, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Matsuo, Yasukazu Noine, Kazuhiko Kasai
  • Patent number: 5097248
    Abstract: An electrode for level detection includes a detection electrode including conductor portions and resistor portions arranged and formed one after the other in a level change direction. An insulating coating layer is formed on either each conductor portion or each resistor portion. The insulating coating layer may be of a film having a property to repel a liquid to be measured.
    Type: Grant
    Filed: January 31, 1990
    Date of Patent: March 17, 1992
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akira Kumada, Kenji Matsuo, Michihiro Murata
  • Patent number: 5083460
    Abstract: A level sensor with an amplifier circuit includes one of the level detection resistor and the temperature compensation resistor as an input resistor or a grounding resistor to the negative input terminal of the operational amplifier, and includes the other resistor as a negative feedback resistor.
    Type: Grant
    Filed: November 26, 1990
    Date of Patent: January 28, 1992
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Akira Kumada, Kenji Matsuo, Chitaka Ochiai
  • Patent number: 5063433
    Abstract: A semiconductor device comprises a first pad region applied with a first potential, a first line led from the first pad region and connected to a first circuit, a second pad region integrated with the first pad region and applied also with the first potential, and a second line led from the second pad region connected to a second circuit and overlapped with the first line.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: November 5, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Matsuo, Tadashi Nonaka, Ikuo Tsuchiya
  • Patent number: 5059838
    Abstract: A delay circuit delays an input signal having a predetermined frequency by a time corresponding to a control signal. A delay amount detector detects a signal delay amount of the delay circuit. A charge pump circuit generates a DC voltage corresponding to a pulse width ratio between the input signal and a detection signal of the delay amount detector. This DC voltage is fed back to the delay circuit as a control signal.
    Type: Grant
    Filed: January 17, 1990
    Date of Patent: October 22, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Motegi, Kenji Matsuo, Akira Nagae, Hideaki Uchida
  • Patent number: 5033300
    Abstract: A device for measuring displacement comprises a pair of sensor elements of which output voltage changes stepwise in dependency upon displacement of a measurement object, a differentiating circuit for detecting time points at which the output voltage of the pair of sensor elements suddenly changes, and a counter for counting the sudden change time points of the output voltage detected by the differentiating curcuit.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: July 23, 1991
    Assignee: Murata Mfg., Co., Ltd.
    Inventors: Kenji Matsuo, Akira Kumada, Michihiro Murata
  • Patent number: 4859970
    Abstract: A voltage controlled oscillator comprises a phase locked loop section and a voltage controlled oscillator section. The phase locked loop section is coupled with an input signal at a reference frequency and a reference potential, and performs a signal feedback control so as to obtain a constant delay time of a first variable delay circuit contained in the phase locked loop section. The voltage controlled oscillator section controls a delay time of a second variable delay circuit in a ring oscillator by a control input voltage and an output voltage of a low-pass filter contained in the phase locked loop section, and produces a signal oscillating at a frequency as determined by the delay time. In the voltage controlled oscillator thus arranged, the output frequency is determined by controlling a delay time of the second variable delay circuit in the voltage controlled oscillator section.
    Type: Grant
    Filed: November 29, 1988
    Date of Patent: August 22, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Matsuo, Ikuo Tsuchiya
  • Patent number: 4716308
    Abstract: A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: December 29, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Matsuo, Itsuo Sasaki, Hiroaki Suzuki, Mitsuyuki Kunieda
  • Patent number: 4656429
    Abstract: A voltage comparison circuit having an amplification circuit which includes an inverting amplifier and a switching MOS transistor for setting an operation point of the inverting amplifier connected between input and output terminals of the inverting amplifier. The amplification circuit further includes at least one low-pass filter connected in a closed loop including the inverting amplifier and the switching MOS transistor.
    Type: Grant
    Filed: January 5, 1983
    Date of Patent: April 7, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Eiji Masuda, Kenji Matsuo
  • Patent number: 4633101
    Abstract: A semiconductor switching circuit includes a MOS inverter and a switching MOS transistor for executing a switching operation in response to the output signal from the MOS inverter. The semiconductor switching circuit further includes a low-pass filter coupled between the MOS inverter and the gate of the switching MOS transistor.
    Type: Grant
    Filed: May 17, 1985
    Date of Patent: December 30, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Eiji Masuda, Kenji Matsuo
  • Patent number: 4600916
    Abstract: A parallel analog-to-digital converter circuit comprises a plurality of level comparator circuits and a plurality of detectors. The level comparator circuits compare the level of one analog input signal with a plurality of reference levels. Any two or more level comparator circuits which receive consecutive reference levels from one set. Each of the detectors determines whether or not the output signals from the level comparator circuits of one set are in a specified state. According to the number of sets of level comparator circuits whose output signals are detected to be in the specified state, it is determined whether or not the analog-to-digital converter circuit functions correctly. the upper limit of the speed of analog-to-digital conversion can be determined according to this number of sets.
    Type: Grant
    Filed: April 21, 1983
    Date of Patent: July 15, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Eiji Masuda, Kenji Matsuo, Yasuhiko Fujita
  • Patent number: 4599522
    Abstract: An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C.sub.mP12, C.sub.mP13, C.sub.mN12, C.sub.mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C.sub.mN11 of the first n channel MOS transistor and the mirror capacitance C.sub.mP11 of the first p channel MOS transistor.
    Type: Grant
    Filed: November 17, 1983
    Date of Patent: July 8, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Matsuo, Fuminari Tanaka
  • Patent number: 4560890
    Abstract: An input voltage sampler samples the difference between two input voltages. An alternate switch switches at a period which is longer than twice the sampling period. The voltage difference is supplied through the alternate switch to a plurality of amplifiers. Prior to starting the amplifying operation, operating point setting circuits set the input level to the amplifiers at the operating point.
    Type: Grant
    Filed: August 26, 1983
    Date of Patent: December 24, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Eiji Masuda, Kenji Matsuo, Yasuhiko Fujita