Abstract: Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.

Abstract: A low pass filter which comprises first, second and third switched capacitor circuits connected to a power source V.sub.DD and/or a power source V.sub.SS, first and second operational amplifiers driven by the power sources V.sub.DD and V.sub.SS, and a bias circuit connected between the power sources V.sub.DD and V.sub.SS for providing a bias voltage to the non-inverting input terminals of the first and second amplifiers.

Abstract: Disclosed is a switched capacitor filter circuit employing the equivalent resistance of a switched capacitor circuit as the resistive element in a frequency dependent impedance converting circuit.

Abstract: An oscillation circuit having a reference voltage circuit for forming a reference voltage by dividing a power supply voltage. The reference voltage circuit supplies the reference voltage to one of the input terminals of the comparing circuit. A charge/discharge voltage is supplied from a junction between a transmission gate circuit and a CR circuit to the other input terminal of the comparing circuit. The comparing circuit compares the charge/discharge voltage with the reference voltage to produce pulse signals.

Abstract: An analog switch device has p- and n-channel metal oxide semiconductor field effect transistors, each having a source electrode, a drain electrode, a gate electrode and a substrate electrode. The p- and n-channel metal oxide semiconductor field effect transistors are connected parallel to each other. First and second analog signals are received and produced at a pair of nodes between the p- and n-channel metal oxide semiconductor field effect transistors. Control signals which are inverted with each other are respectively supplied to the gate electrodes of the p- and n-channel metal oxide semiconductor field effect transistors. A voltage buffer circuit is provided for applying a predetermined voltage to the substrate electrode of one of the p- and n-channel metal oxide semiconductor field effect transistors so as to decrease a change in a threshold voltage due to the source-substrate bias effect.

Abstract: A signal level comparing circuit includes a comparator operated by a power source voltage and impressed with a reference voltage lower than the power source voltage at a non-inverted input terminal, first and second resistors connected at one end to the inverted input terminal of the comparator. The other end of the second resistor is grounded through an MOS transistor whose gate is connected to the output terminal of the comparator. The signal level comparing circuit further includes a resistor which is connected at one end to the inverted input terminal of the comparator and grounded through an MOS transistor whose gate is connected to the output terminal of the comparator through an inverter.

Abstract: An operational amplifier which comprises a first amplifying circuit; a second amplifying circuit which is connected to the first amplifying circuit and carries out inverting amplification; a third amplifying circuit which is connected to the second amplifying circuit, carries out noninverting amplification and has a gain of substantially 1; a first feedback circuit which is connected between the output and input terminals of the second amplifying circuit and carries out phase-compensation; and a second feedback circuit which is connected between the output terminal of the third amplifying circuit and the input terminal of the second amplifying circuit, and carries out phase-compensation.

Abstract: The invention provides an inverting amplifier having a CMOS inverter and a MOSFET, the latter being connected to an input-output path of the CMOS inverter to autozero the CMOS inverter to its toggle point upon being turned on. An output signal from a CMOS inverter which has a short-circuited input-output path is supplied to the back gate of the MOSFET. Even if a gate threshold voltage of the MOSFET varies, its ON resistance is kept substantially constant.

Abstract: A semiconductor analog switch circuit device is disclosed in which a second analog switch circuit is connected in parallel with a first analog switch circuit. The first and second switch circuits are controlled by control pulses with opposite phases. An input signal is applied to one of the parallel junctions of the first and second analog switch circuits, while an output signal is derived from the other parallel junction.

Abstract: A logic gate section of a Schmitt trigger circuit has first and second nodes to which variable bias voltages are applied. A first bias control IGFET is connected between the first node and a first potential terminal. A second bias control IGFET is connected between the first node and a second potential terminal. A third bias control IGFET is connected between the second node and the first potential terminal. A fourth bias control IGFET is connected between the second node and the second potential terminal. A control signal to the gates of the first and fourth bias control IGFET's is provided by the Schmitt trigger input signal and the control signal to each of the gates of the third and fourth bias control IGFET's is provided by the Schmitt trigger feedback connection of two series-connected inverters.

Abstract: A CR oscillation circuit is provided which includes inverters which are connected in series and whose operating current paths between a power source terminal and a ground terminal are connected in series with a constant current source. In certain embodiments, a resistor is connected between the output terminal of one inverter and the input terminal of the first inverter, and a capacitor is connected between the output terminal of another inverter and the input terminal of the first inverter. The CR oscillation circuit further has a constant current source connected in series with the operating current path of said inverters between the power source terminal and the ground terminal. In other embodiments, the resistor and capacitor are connected in parallel and to the input of an inverter.

Abstract: A semiconductor integrated circuit device, which comprises:transistors constituting a plurality of series-connected logic circuits, wherein some of the mutually-facing or paired transistors of every two adjacent series-connected logic circuits or at least one pair thereof are so connected as to span said two adjacent circuits with a common gate provided between said paired transistors;conductors for connecting the source electrodes and/or the drain electrodes of said spanning paired transistors; anda plurality of signal generators for supplying required signals to the respective transistors, and whereby a MOS type logic circuit constructed by arranging those of the transistors which are supplied with a synchronizing signal closer to the output terminal than those of the transistors which are supplied with an input signal can be accelerated in operation.