Electroplated interconnection structures on integrated circuit chips
A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
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The present application is a continuation-in-part of co-pending U.S. patent application Ser. No. 08/670,200, filed Jun. 21, 1996, and entitled “Electroplated Interconnection Structures on Integrated Circuit Chips” and claims priority to co-pending U.S. provisional application Ser. No. 60/009,538 filed Dec. 29, 1995.
This application is cross referenced to U.S. patent application Ser. No. 08/495,249 filed Jun. 27, 1995, by P. Andricacos et al., entitled “Copper Alloys for Chip and Package Interconnections and Method of Making,” which is directed to copper alloys for chip and package interconnections with about 0.01 to about 10 weight percent of carbon, indium and/or tin.
FIELD OF THE INVENTIONThis invention relates to interconnection wiring on electronic devices such as on integrated circuit (IC) chips and more particularly to void-free and seamless submicron structures fabricated by Cu electroplating from baths that contain additives conventionally used to produce bright, level, low-stress deposits.
BACKGROUND OF THE INVENTIONAlCu and its related alloys are a preferred alloy for forming interconnections on electronic devices such as integrated circuit chips. The amount of Cu in AlCu is typically in the range from 0.3 to 4 percent.
Replacement of AlCu by Cu and Cu alloys as a chip interconnection material results in advantages of performance. Performance is improved because the resistivity of Cu and certain copper alloys is less than the resistivity of AlCu; thus narrower lines can be used and higher wiring densities will be realized.
The advantages of Cu metallization have been recognized by the entire semi-conductor industry. Copper metallization has been the subject of extensive research as documented by two entire issues of the Materials Research Society (MRS) Bulletin, one dedicated to academic research on this subject in MRS Bulletin, Volume XVIII, No. 6 (June 1993) and the other dedicated to industrial research in MRS Bulletin, Volume XIX, No. 8 (August 1994). A 1993 paper by Luther et al., Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices, in PROC. IEEE VLSI MULTILEVEL INTERCONNECTIONS CONF., Santa Clara, Calif., Jun. 8-9, 1993, p. 15, describes the fabrication of Cu chip interconnections with four levels of metallization.
Processes such as Chemical Vapor Deposition (CVD) and electroless plating are popular methods for depositing Cu. Both methods of deposition normally produce at best conformal deposits and inevitably lead to defects (voids or seams) in wiring especially when trenches have a cross section narrower at the top than at the bottom as a result of lithographic or reactive ion etching (RIE) imperfections. Other problems of CVD have been described by Li et al., Copper-Based Metallization in ULSI Structures—Part II: Is Cu Ahead of its Time as an On-chip Material?, MRS BULL., XIX, 15 (1994). In electroless plating, while offering the advantage of low cost, the evolution of hydrogen during metal deposition leads to blistering and other defects that are viewed as weaknesses for industry wide implementation.
An electroplating process for depositing copper, silver or gold onto a semiconductor wafer is described in U.S. Pat. No. 5,256,274 ('274), which issued on Oct. 26, 1993, to J. Poris. In
A process is described for fabricating a low cost, highly reliable Cu interconnect structure for wiring in integrated circuit chips with void-free seamless conductors of sub-micron dimensions. The process comprises deposition of an insulating material on a wafer, lithographically defining and forming sub-micron trenches or holes in the insulating material into which the conductor will be deposited to ultimately form lines or vias, depositing a thin conductive layer serving as a seed layer or plating base, depositing the conductor by electroplating from a bath containing additives and planarizing or chemical-mechanical polishing the resulting structure to accomplish electrical isolation of individual lines and/or vias.
The invention further provides a process for fabricating an interconnect structure on an electronic device comprising the steps of forming a seed layer on a substrate having insulating regions and conductive regions, forming a patterned resist layer on the seed layer, electroplating conductor material on the seed layer not covered by the patterned resist from a bath containing additives, and removing the patterned resist.
The invention further provides a process for fabricating an interconnect structure on an electronic device with void-free seamless conductors comprising the steps of forming an insulating material on a substrate, lithographically defining and forming lines and/or vias in which interconnection conductor material will be deposited, forming a conductive layer serving as a plating base, forming a patterned resist layer on the plating base, depositing the conductor material by electroplating from a bath containing additives, and removing the resist.
The invention further provides a process for fabricating an interconnect structure on an electronic device comprising the steps of forming a seed layer on a substrate having insulating regions and conductive regions, forming a blanket layer of conductor material on the seed layer from a bath containing additives, forming a patterned resist layer on the blanket layer, removing the conductor material where not covered by the patterned resist, and removing the patterned resist. The invention further provides a conductor for use in interconnections on an electronic device comprising Cu including small amounts of a material in the Cu selected from the group consisting of C (less than 2 weight percent), O (less than 1 weight percent), N (less than 1 weight percent), S (less than 1 weight percent), and Cl (less than 1 weight percent) formed by electroplating from a bath containing additives.
The interconnection material may be Cu electroplated from baths that contain additives conventionally used to produce bright, level, low-stress deposits. The rate of Cu electroplating from such baths is higher deep within cavities than elsewhere. This plating process thus exhibits unique superfilling properties and results in void-free seamless deposits that cannot be obtained by any other method. Interconnection structures made by Cu electroplated in this manner, are highly electromigration-resistant with an activation energy for electromigration equal to or greater than 1.0 eV. The conductor is composed substantially of Cu and small amounts of atoms and/or molecular fragments of C (less than 2 weight percent), O (less than 1 weight percent), N (less than 1 weight percent), S (less than 1 weight percent), and Cl (less than 1 weight percent).
Cu which is highly electromigration-resistant is electroplated from plating solutions that contain additives conventionally used to produce bright, ductile, and low-stress plated deposits.
It is an object of the present invention to electroplate conductors of Cu such as interconnect wiring without leaving a seam or a void in the center of the conductor.
It is a further object of the present invention to electroplate conductors of Cu with substantially uniform filling thickness where the conductors have a difference in widths such as less than 1 micron and greater than 10 microns. The depth to width ratio of a conductor may be equal to or greater than 1. The depth to width ratio of a via may exceed 1.
It is a further object of the present invention to lower the manufacturing cost of integrated circuits by the combined effects of 1) blanket deposition of Cu by electrolytic plating, 2) dual damascene fabrication (an approach in which two levels of metallization are fabricated in a single blanket-deposition step), and 3) the ability to planarize the upper surface by processes such as chemical mechanical polishing.
BRIEF DESCRIPTION OF THE DRAWINGSThese and other features, objects, and advantages of the present invention will become apparent upon consideration of the following detailed description of the invention when read in conjunction with the drawing in which:
A Damascene plating process is one in which plating is done over the entire wafer surface and is followed by a planarization process that isolates and defines the features. Plating is preceded by the deposition of a plating base over the entire wiring pattern that has been defined lithographically. Layers that improve adhesion and prevent conductor/insulator interactions and diffusion are deposited between the plating base and the insulator. A schematic representation of the process is shown in
In order to avoid the formation of a void or seam in Cu 6, the rate of electroplating should be higher at low or deep points within the feature than elsewhere. This is illustrated in
Superfilling by the use of additives in the plating bath makes it possible to create void-free and seamless lines and vias even if the lithographic process produces features or cavities 22 in a dielectric layer 1 that are narrower at the top than at the bottom as shown in
Copper plating from solutions incorporating additives conventionally used to produce level deposits on a rough surface can be used to accomplish superfilling required to fill sub-micron cavities. One suitable system of additives is the one marketed by Enthone-OMI, Inc., of New Haven, Conn. and is known as the SelRex Cubath M system. The above additives are referred to by the manufacturer as MHy. Another suitable system of additives is the one marketed by LeaRonal, Inc., of Freeport, N.Y., and is known as the Copper Gleam 2001 system. The additives are referred to by the manufacturer as Copper Gleam 2001 Carrier, Copper Gleam 2001-HTL, and Copper Gleam 2001 Leveller. And another suitable system of additives is the one marketed by Atotech USA, Inc., of State Park, Pa., and is known as the Cupracid HS system. The additives in this system are referred to by the manufacturer as Cupracid Brightener and Cupracid HS Basic Leveller.
Examples of specific additives which may be added to a bath in the instant invention are described in several patents. U.S. Pat. No. 4,110,176, which issued on Aug. 29, 1978, to H-G Creutz deceased et al., entitled “Electrodeposition of Copper” described the use of additives to a plating bath such as poly alkanol quaternary-ammonium salt which formed as a reaction product to give bright, highly ductile, low stress and good leveling copper deposits from an aqueous acidic copper plating bath which patent is incorporated herein by reference.
U.S. Pat. No. 4,376,685, which issued on Mar. 15, 1983, to A. Watson, entitled “Acid Copper Electroplating Baths Containing Brightening and Leveling Additives,” described additives to a plating bath such as alkylated polyalkyleneimine which formed as a reaction product to provide bright and leveled copper electrodeposits from an aqueous acidic bath which patent is incorporated herein by reference.
U.S. Pat. No. 4,975,159, which issued on Dec. 4, 1990, to W. Dahms, entitled “Aqueous Acidic Bath for Electrochemical Deposition of a Shiny and Tear-free Copper Coating and Method of Using Same,” described adding to an aqueous acidic bath combinations of organic additives including at least one substituted alkoxylated lactam as an amide-group-containing compound in an amount to optimize the brightness and ductility of the deposited copper, which patent is incorporated herein by reference. In U.S. Pat. No. 4,975,159, Table I lists a number of alkoxylated lactams which may be added to a bath in the instant invention. Table II lists a number of sulfur-containing compounds with water-solubilizing groups such as 3-mercaptopropane-1-sulfonic acid which may be added to a bath in the instant invention. Table III lists organic compounds such as polyethylene glycol which may be added to a bath as surfactants in the instant invention.
U.S. Pat. No. 3,770,598, which issued on Nov. 6, 1973, to H-G Creutz, entitled “Electrodeposition of Copper from Acid Baths,” describes baths for obtaining ductile, lustrous copper containing therein dissolved a brightening amount of the reaction product of polyethylene imine and an alkylating agent to produce a quaternary nitrogen, organic sulfides carrying at least one sulfonic group, and a polyether compound such as polypropylene glycol, which patent is incorporated herein by reference.
U.S. Pat. No. 3,328,273, which issued on Jun. 27, 1967, to H-G Creutz et al., entitled “Electrodeposition of Copper from Acidic Baths,” describes copper sulfate and fluoborate baths for obtaining bright, low-stress deposits with good leveling properties that contain organic sulfide compounds of the formula XR1—(Sn)—R2—SO3H, where R1 and R2 are the same or different and are polymethylene groups or alkyne groups containing 1-6 carbon atoms, X is hydrogen or a sulfonic group, and n is an integer of 2-5 inclusive, which patent is incorporated herein by reference. Additionally these baths may contain polyether compounds, organic sulfides with vicinal sulphur atoms, and phenazine dyes. In U.S. Pat. No. 3,328,273, Table I lists a number of polysulfide compounds which may be added to a bath in the instant invention. Table II lists a number of polyethers which may be added to a bath in the instant invention.
Additives may be added to the bath for accomplishing various objectives. The bath may include a copper salt and a mineral acid. Additives may be included for inducing in the conductor specific film microstructures including large grain size relative to film thickness or randomly oriented grains. Also, additives may be added to the bath for incorporating in the conductor material molecular fragments containing atoms selected from the group consisting of C, O, N, S and Cl whereby the electromigration resistance is enhanced over pure Cu. Furthermore, additives may be added to the bath for inducing in the conductor specific film microstructures including large grain size relative to film thickness or randomly oriented grains, whereby the electromigration behavior is enhanced over non-electroplated Cu.
Similar superfilling results are obtained from a solution containing cupric sulfate in the rate from 0.1 to 0.4M, sulfuric acid in the range from 10 to 20% by volume, chloride in the range from 10 to 300 ppm, and LeaRonal additives Copper Gleam 2001 Carrier in the range from 0.1 to 1% by volume, Copper Gleam 2001-HTL in the range from 0.1 to 1% by volume, and Copper Gleam 2001 Leveller in the range 0 to 1% by volume. Finally, similar superfilling results are obtained from a solution containing cupric sulfate, sulfuric acid, and chloride in the ranges mentioned above and Atotech additives Cupracid Brightener in the range from 0.5 to 3% by volume and Cupracid HS Basic Leveller in the range from 0.01 to 05% by volume.
The plating processes described thus far with additives produce superfilling of submicron, high-aspect-ratio features or cavities when performed in conventional plating cells, such as paddle plating cells described in U.S. Pat. Nos. 5,516,412, 5,312,532, which issued on May 17, 1994 to P. Andricacos et al., and U.S. Pat. No. 3,652,442. However, a further benefit described below is realized when the process is performed in a plating cell in which the substrate surface is held in contact only with the free surface of the electrolyte, for example a cup plating cell described in U.S. Pat. No. 4,339,319, which issued Jul. 13, 1982, to S. Aigo, which is incorporated herein by reference. The benefit here is the superfilling of wide cavities in the range from 1 to 100 microns, which may be present among the narrow (submicron) features or cavities.
In a plating cell in which the substrate is submerged in the electrolyte, wide features in the range from 1 to 100 microns will fill more slowly than do narrow features having a width less than 1 micron, such as about 0.1 and above; hence wide features necessitate both a longer plating time and a longer polishing time to produce a planarized structure with no dimples or depressions on the top plated surface.
In contrast in a cup plating cell, when the substrate surface to be plated is held in contact with the meniscus of the electrolyte during plating, cavities of greatly different widths such as less than 1 micron and greater than 10 microns are filled rapidly and evenly at the same rate.
The meniscus of the electrolyte is the curved upper surface of a column of liquid. The curved upper surface may be convex such as from capillarity or due to liquid flow such as from an upwelling liquid.
In
In
The electroplated Cu metal 66 shown in
The grain size of electroplated Cu is generally larger than that produced by other Cu deposition techniques (see
The crystallographic orientation (also known as texture) of plated Cu is substantially more random than that of non-plated Cu films (see
The electromigration resistance of electroplated Cu and pure Cu is a function of the activation energy as measured by the methods referred to in MRS Bulletin, Volume XVIII, No. 6 (June 1993), and Volume XIX, No. 8 (August 1994) which are incorporated herein by reference. The activation energy of electroplated Cu is equal to or greater than 1.0 eV. In addition,
The value of the present invention extends beyond implementation in damascene structures. The increased resistance to electromigration, associated with the presence of atoms and/or molecular fragments containing C, O, N, S, and Cl, is similarly beneficial in conductor elements that are fabricated by through-mask plating on a planar base as shown in
The process for through-mask plating on a planar base is shown in
The process for through-mask plating on an excavated base is shown in
The process for blanket plating followed by pattern etching is shown in
In
While there has been described and illustrated a process for fabricating an interconnect structure on an electronic device and a Cu conductor having electromigration resistance due to atoms and/or molecular fragments of C, O, N, S, and Cl, and specific microstructural features such as large grains size relative to film thickness and a random crystallographic orientation, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.
Claims
1. A structure for use in interconnections on an electronic device comprising:
- a dielectric layer having a substantially planar upper surface and having a pattern of recesses therein,
- the recesses having a width at the upper surface less than one micrometer,
- the recesses being filled with a conductor material that is seamless and/or void-free; and
- wherein the conductor material comprises substantially copper.
2. The structure of claim 1 wherein the recesses have a depth to width ratio equal to or greater than 1.
3. The structure of claim 1 further including a metal liner between the conductive layer and the dielectric layer in the recesses.
4. The structure of claim 1 wherein the copper includes small amounts of a material in said copper selected from the group consisting of C (less than 2 weight percent), O (less than 1 weight percent), N (less than 1 weight percent), S (less than 1 weight percent), and Cl (less than 1 weight percent).
5. The structure of claim 1 wherein the copper includes specific film microstructures including large grain size relative to film thickness and/or randomly oriented grains.
6. The structure of claim 5 wherein the small amounts of material include atoms and/or molecular fragments.
7. The structure of claim 1 wherein the conductor has an activation energy for electromigration equal to or greater than 1.0 eV and further includes specific film microstructures including large grain size relative to film thickness and/or randomly oriented grains.
8. The structure of claim 1 wherein the conductor material further includes positive amounts of atoms and/or molecular fragments containing atoms selected from the group consisting of C, O, N, S, and Cl.
9. The structure of claim 8 wherein the electromigration resistance of the copper is enhanced over pure copper.
10. The structure of claim 1 which comprises a double damascene structure.
11. The structure of claim 1 wherein each of the recesses has a bottom surface and side surfaces intersecting the bottom surface, and wherein the conductor material is deposited on the bottom surface and side surfaces.
12. The structure of claim 11 wherein the bottom surface of each recess is substantially horizontal with respect to a major plane of the substrate.
13. A process for fabricating an interconnect structure on an electronic device with void-free seamless submicron conductors comprising the steps of:
- forming an insulating material on a substrate,
- lithographically defining and forming recesses for submicron lines and/or submicron vias in said insulating material in which interconnection conductor material will be deposited,
- forming a conductive layer in said recesses serving as a plating base,
- forming a through-mask,
- depositing by a through-mask plating process said conductor material in a seamless and void-free manner by electroplating from a bath containing additives, said bath additives causing the plating rate to increase with depth along the sidewall of a recess, thereby preventing the formation of a seam or void in a conductor in said recesses, and wherein said conductor material comprising copper.
14. The process of claim 13 wherein said step of depositing includes depositing Cu as said conductor material.
15. The process of claim 13 further including the step of adding additives to said bath for incorporating in said conductor material positive amounts of atoms and/or molecular fragments containing atoms selected from the group consisting of C, O, N, S, and Cl.
16. The process of claim 13 further including the step of adding additives to said bath for inducing in said conductor specific film microstructures including large grain size relative to film thickness and/or randomly oriented grains.
17. The process of claim 13 further including the step of adding additives to said bath for incorporating in said conductor material molecular fragments containing atoms selected from the group consisting of C, O, N, S and Cl whereby the electromigration resistance is enhanced over pure Cu.
18. The process of claim 13 further including the step of adding additives to said bath for inducing in said conductor specific film microstructures including large grain size relative to film thickness and/or randomly oriented grains whereby the electromigration behavior is enhanced over non-electroplated Cu.
19. The process of claim 13 wherein the depth to width ratio of a conductor is equal to or greater than 1.
20. The process of claim 13 wherein the depth to width ratio of a via exceeds 1.
21. The process of claim 20 wherein the depth to width ratio of a conductor is equal to or greater than 1.
22. The process of claim 13 wherein said step of depositing further includes the step of placing the upper surface of said substrate in contact with the surface of said bath.
23. The process of claim 22 wherein said step of depositing further includes flowing said bath at said surface of said bath.
24. The process of claim 13 wherein said step of depositing further includes the step of electroplating using a cup plater.
25. The process of claim 13 further including the step of electroplating from a plating solution comprising a copper salt, a mineral acid, and one or more additives selected from the group consisting of an organic sulfur compound with water solubilizing groups, a bath-soluble oxygen-containing compound, a bath-soluble polyether compound, or a bath-soluble organic nitrogen compound that may also contain at least one sulfur atom.
26. The process of claim 25 wherein said plating solution contains small amounts of a chloride ion in the range from 10 to 300 parts per million.
27. The process of claim 25 wherein said Cu salt is cupric sulfate.
28. The process of claim 25 wherein said mineral acid is sulfuric acid.
29. The process of claim 30 wherein said organic sulfur compound carries at least one sulfonic group.
30. The process of claim 25 wherein said organic sulfur compound has at least two sulfur atoms that are vicinal.
31. The process of claim 31 wherein said organic sulfur compound has at least two sulfur atoms that are vicinal and carries at least one terminal sulfonic group.
32. The process of claim 25 wherein said organic sulfur compound is selected from the group consisting of mercaptopropane sulfonic acid, thioglycolic acid, mercaptobenzthiozol-S-propansulfonic acid and ethylenedithiodipropyl sulfonic acid, dithiocarbamic acid, alkali metal salts of said compounds, and amine salts of said compounds.
33. The process of claim 25 wherein said organic sulfur compound has the formula X—R1—(Sn)—R2—SO3H where the R groups are the same or different and contain at least one carbon atom, X is selected from the group consisting of a hydrogen and a sulfonic group, and n is 2-5 inclusive.
34. The process of claim 25 wherein said oxygen-containing compound is selected from the group consisting of polyethylene glycol, and carboxymethylcellulose.
35. The process of claim 26 wherein said organic nitrogen compound is selected from the group containing pyridines and substituted pyridines, amides, quaternary ammonium salts, imines, phthalocyanines and substituted phthalocyanines, phenazines, and lactams.
36. The process of claim 13 wherein said process preferentially deposits said conductor material in corners at a bottom of said recesses defined in said insulating material.
37. The process of claim 13 wherein the additives are polarizing.
38. The process of claim 37 wherein the bottom surface of each recess intersects the side surfaces at a 90° angle.
39. The process of claim 38 wherein the bottom surface of each recess is substantially horizontal with respect to a major plane of the substrate.
Type: Application
Filed: Jun 29, 2005
Publication Date: Jan 26, 2006
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Panayotis Andricacos (Croton-on-Hudson, NY), Hariklia Deligianni (Tenafly, NJ), John Dukovic (Pleasantville, NY), Daniel Edelstein (White Plains, NY), Wilma Horkans (Ossining, NY), Chao-Kun Hu (Somers, NY), Jeffrey Hurd (Marlboro, NY), Kenneth Rodbell (Sandy Hook, CT), Cyprian Uzoh (Hopewell Junction, NY), Kwong-Hon Wong (Wappingers Falls, NY)
Application Number: 11/168,559
International Classification: H01L 23/48 (20060101); H01L 21/44 (20060101);