Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Abstract: Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.

Abstract: Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Abstract: Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Abstract: Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus.

Abstract: Insulating a via in a semiconductor substrate, including: applying a first dielectric layer to the semiconductor substrate; and applying a second dielectric layer to the semiconductor substrate, wherein the second dielectric layer is applied on the first dielectric layer, wherein the second dielectric layer is more conformal than the first dielectric layer.

Abstract: Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Abstract: Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.

Abstract: Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.

Abstract: Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus.

Abstract: A semiconductor structure having a through semiconductor via (TSV) which includes a semiconductor wafer of a semiconductor material and having a front side and a back side; front end of the line (FEOL) components; an insulative annulus extending from the front side to the back side, the insulative annulus having a center including the semiconductor material such that the semiconductor material in the center of the insulative annulus is recessed from the back side to form a recess; a metal filling the recess; a through silicon via (TSV) extending in a straight line from the metal-filled recess, through the center of the semiconductor material in the center of the insulative annulus and into the FEOL components such that there is semiconductor material between the TSV and the insulative annulus.

Abstract: A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Abstract: A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

Abstract: In a method for controlling pricing of a product, a radio frequency identification (RFID) tag having at least one processor is attached to a monitored product. A value indicative of a degree of exposure to an environmental condition is obtained. The obtained value is compared with a predetermined value range. A price of the monitored product is adjusted when the result of the comparison falls outside the predetermined value range.

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal.