Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: A method for characterizing the electronic properties of a solar cell to be used in a photovoltaic module comprises the steps of performing a room temperature IV curve measurement of the solar cell and classifying the solar cell based on this IV curve measurement. In order to take stress-related effects into account, the solar cells are reclassified depending on the result of an additional measurement conducted on the solar cells under stress. This stress-related measurement may be gained from light induced thermography (LIT) yielding information on diode shunt areas within the solar cell.

Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

Abstract: Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.

Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

Abstract: A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.

Abstract: A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.

Abstract: A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.

Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.

Abstract: The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.

Abstract: A photovoltaic module (10) comprises a plurality of solar cells (20) interconnected in serial arrays (15). At least some of the solar cells (20) are equipped with control units (30) comprising at least one thermal sensor (42) and one power sensor (43). The control unit (30) comprises means (35) for removing a specific solar cell (20?) from the photovoltaic module (10) network if said solar cell (20?) is found to have reached a predefined level of degradation. In a preferred embodiment, control unit (30) is an ASIC chip (40) in thermal contact with said solar cell (20) and electrically connected to said solar cell (20).

Abstract: A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).

Abstract: A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.

Abstract: A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

Abstract: A microelectronic assembly and related method of forming a through hole extending through a first wafer and a second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers. A hole can be etched downwardly through the first wafer until a gap is partially exposed between the confronting faces of the first and second wafers. The hole can have a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening through which the interfacial gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered such that at least some of the sputtered material deposits onto at least one of the exposed confronting faces of the first and second wafers and provides a wall between the confronting faces.

Abstract: A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

Abstract: The invention relates to a method for assembly of solar cell modules by arranging a multitude pre-manufactured, individualized solar cells for forming a matrix of solar cells for the solar cell module; depositing a metallization layer at least partially on at least one surface of the matrix of solar cells for forming the solar cell module; testing electrical function at least of the solar cell module; depositing a passivation layer on a surface of the solar cell module. In another aspect the invention relates to a manufacturing system for a solar cell module and a solar cell module (26) comprising a matrix of pre-manufactured and individualized solar cells and manufactured according to the aforementioned method.

Abstract: A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated.