Abstract: A method of operating a memory device comprises applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining whether a read failure occurs with respect to one or more of the memory cells, upon determining that a read failure has occurred with respect to some of the memory cells, determining threshold voltage distribution information for distinct groups of the memory cells, and determining a new read voltage to be applied to the selected wordline based on the threshold voltage distribution information.

Abstract: A memory device includes a memory cell array and a page buffer unit. The memory cell array includes multiple memory cells. The page buffer unit performs a logic operation on data sequentially read from the memory cells at different voltage levels, based on the read data and a read direction of applying the different voltage levels.

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: A memory device comprises a memory cell that is in one of an erase state and first through N-th program states (N>2). The memory device can be read by determining a first read voltage between the erase state and the first program state based on variations of respective threshold voltage distributions of the erase state and the first program state, and determining one among second through N-th read voltages based on variations in respective threshold voltage distributions of two adjacent program states among the first through N-th program states, and determining remaining read voltages among the second through N-th read voltages based on the one read voltage.

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips.

Abstract: A semiconductor memory device for performing additional error correction code (ECC) correction according to a cell pattern and an electronic system including the same are provided. The semiconductor memory device includes a memory cell array configured to store user data; and an ECC engine configured to perform first ECC encoding on the user data, output a result of the first ECC encoding as ECC information, detect a predetermined cell pattern based on the user data, and additionally perform second ECC encoding on data of a cell corresponding to the predetermined cell pattern detected. Accordingly, data errors that may occur due to a certain cell pattern are prevented.

Abstract: Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a bending portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the bending portion within a resin application portion, crack occurred in a narrow wiring width can be avoided. The tape may include a first lead and a second lead formed on a dielectric substrate and a bending portion formed on one of the first lead and the second lead wherein the bending portion is formed within a resin application portion.

Abstract: A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command.

Abstract: An HA-protein conjugate in which an HA-aldehyde derivative, in which an aldehyde group is introduced to a hyaluronic acid or a salt thereof, is conjugated to the N-terminus of a protein, and a method for preparing the same are provided. The HA-protein conjugate includes a protein drug exhibiting an excellent bioconjugation efficiency and long-term medicinal effects, and has excellent protein drug activities since the hyaluronic acid is specifically conjugated to the N-terminus of the protein. Also, since liver-targeting properties of the hyaluronic acid can be freely controlled by changing an aldehyde substitution rate of the HA-aldehyde derivative, the HA-protein conjugate can be effectively used as a protein drug for treating liver diseases, and also be useful in enabling long-term medicinal effects of a protein drug required to bypass the liver. Accordingly, the HA-protein conjugate can be effectively used for a drug delivery system of proteins.

Abstract: A method for selectively growing a nitride semiconductor, in which a mask is formed, with an opening formed therein, on a nitride semiconductor layer. A nitride semiconductor crystal is selectively grown on a portion of the nitride semiconductor layer exposed through the opening in the mask, the nitride semiconductor crystal shaped as a hexagonal pyramid and having crystal planes inclined with respect to a top surface of the nitride semiconductor. Here, the nitride semiconductor crystal has at least one intermediate stress-relieving area having crystal planes inclined at a greater angle than those of upper and lower areas of the nitride semiconductor crystal, the intermediate stress-relieving area relieving stress which occurs from continuity in the inclined crystal planes.

Abstract: A flash memory device performs a program operation using an incremental step pulse programming (ISPP) scheme comprising a plurality of program loops. In each of the program loops, a program pulse operation is performed to increase the threshold voltages of selected memory cells, and a program verify operation is performed to verify a program status of the selected memory cells. The program verify operation can be selectively skipped in some program loops based on a voltage increment of one or more of the program pulse operations, an amount by which threshold voltages of the selected memory cells are to be increased in the ISPP scheme, or a total number of program loops of the ISPP scheme.

Abstract: A method of programming a nonvolatile memory device comprises programming memory cells by performing a plurality of program loops with bitline precharging inactivated during program verification operations of some of the program loops, and with bitline precharging activated during program verification operations of some of the program loops.

Abstract: A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table.

Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.

Abstract: This disclosure relates to a micro manipulator having a simple structure and having high possibility of recording a biological signal of a neuron at a desired position by improving positioning resolution of an electrode disposed adjacent to a subject's brain neuron or an electrode holder attached with the electrode. The micro manipulator according to the disclosure includes: a motor which includes a shaft and a vibration portion; a mobile which is connected to the shaft so as to be movable along the shaft; and a frame which supports the motor, wherein an electrode is connected to the mobile in a direction parallel to a longitudinal direction of the shaft, and wherein when the mobile moves linearly in accordance with a vibration of the shaft due to the vibration portion, the electrode moves linearly.

Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.

Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.