Patents by Inventor Kohichi Nakamura

Kohichi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9344652
    Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 17, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
  • Patent number: 9307174
    Abstract: A solid-state imaging apparatus includes a plurality of pixels arrayed in a matrix, and configured to generate signals by photoelectric conversion; a plurality of read-out circuits disposed on each column of the plurality of pixels arrayed in a matrix pattern, and configured to read out the signals from the plurality of pixels; a plurality of comparison units configured to compare the signals output from the plurality of read-out circuits with a reference signal whose level changes with time; a counter configured to count a clock signal after the level of the reference signal starts a change; a storage unit configured, when a magnitude relationship between the signals output from the plurality of the read-out circuits and the reference signal is reversed; and a reset unit configured to reset the count value stored in the storage unit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Hiroki Hiyama, Kazuhiro Saito, Kohichi Nakamura, Yu Maehashi
  • Publication number: 20160028980
    Abstract: After a signal level of a digital signal is changed in a period in which a plurality of memories is sampling the digital signal, a signal for causing the plurality of memories to hold the digital signal being sampled by the plurality of memories is supplied to the plurality of memories.
    Type: Application
    Filed: June 3, 2015
    Publication date: January 28, 2016
    Inventors: Hiroaki Kameyama, Hiroki Hiyama, Kohichi Nakamura
  • Patent number: 9232165
    Abstract: A solid-state imaging apparatus includes: a ramp signal generator for generating first and second time-changing ramp signals during first and second analog-to-digital conversion periods, respectively; comparators for comparing a reset signal of a pixel with the first ramp signal during the first analog-to-digital conversion period, and comparing a pixel signal with the second ramp signal during the second analog-to-digital conversion period; and memories for storing, as first and second digital data, count values of counting from a start of changing the first and second ramp signals until an inversion of outputs of the comparators, during the first and second analog-to-digital conversion periods, wherein the ramp signal generator supplies a current from a current generator to a first capacitor element by a sampling and holding operation of a switch, and generates the first and second ramp signals based on the same bias voltage held by the first capacitor element.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura
  • Patent number: 9204072
    Abstract: A photoelectric conversion device includes a pixel array including a plurality of pixels arranged in a matrix, a plurality of blocks including a plurality of pairs, each of the pairs including a comparator provided correspondingly with a column in the pixel array and a memory provided correspondingly with the comparator, and a block information supply unit configured to supply block information which indicates a location of a block, to the plurality of memories included in the blocks.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 1, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Hiyama, Kohichi Nakamura, Kazuo Yamazaki, Kazuhiro Saito
  • Publication number: 20150296163
    Abstract: An image capturing apparatus includes: plural pixels arranged in matrix, each outputting a signal from a photoelectric conversion element; and plural readout circuits each provided for a corresponding column of the pixels, signals from the pixels being input to the readout circuits. The readout circuit includes an amplifier unit configured to amplify the signal from the pixel, and have a variable gain, and a hold capacitance connected to an output terminal of the amplifier unit via a sampling switch, and having a variable capacitance value. When the variable gain of the amplifier unit is set to be a first gain, the variable capacitance value of the hold capacitance is set to be a first capacitance value. When the variable gain is set to be a second gain larger than the first gain, the variable capacitance value is set to be a second capacitance value smaller than the first capacitance value.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 15, 2015
    Inventors: Kohichi Nakamura, Tetsuya Itano, Hideo Kobayashi
  • Patent number: 9131178
    Abstract: A solid-state imaging apparatus that shortens a time for reading out pixel signals of all pixels and improves the aperture ratio of pixels is provided. The solid-state imaging apparatus includes a plurality of pixels (3) arranged in a matrix along a plurality of rows and columns, in which each of the pixels includes a photoelectric conversion element and a color filter; a plurality of buffers (2) arranged with each one corresponding to a plurality of pixels; and a plurality of vertical output lines (1) arranged such that two or more of the vertical output lines (1) are arranged correspondingly to one of the columns of the pixels; in which an input node of each of the buffers is connected commonly to a plurality of pixels having color filters of different colors, and output nodes of the plurality of buffers are connected alternately to a plurality of vertical output lines.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 8, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohichi Nakamura, Hiroki Hiyama
  • Patent number: 9118857
    Abstract: A solid-state imaging apparatus includes: a plurality of first unit pixels configured to generate a signal by a photoelectric conversion; a first output line connected to the plurality of first unit pixels; and a first amplifier configured to amplify a signal from the first output line, wherein the first amplifier includes an operational amplifier (401), an initializing switch (404) having one terminal connected to an output terminal of the operational amplifier, and an offset adjusting unit (402) connected between the other terminal of the initializing switch and an input terminal of the operational amplifier, and the offset adjusting unit has a transistor having a source and a drain connected to each other.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: August 25, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichiro Iwata, Kazuhiro Saito, Kohichi Nakamura, Takeshi Akiyama
  • Publication number: 20150237286
    Abstract: A solid-state imaging apparatus includes: a comparator comparing a signal output from pixels with a reference signal of which level changes dependent on time; a plurality of first bit storage units and a plurality of second bit storage units holding, bit by bit, a count signal of the plurality of bits from a counter, according to a write control signal based on a result of the comparing by the comparator; and a control unit arranged between the comparator and the first and second bit storage units, and adjusting a delay time of the write control signal. An order of lengths of the delay time of the count signal held by the first and second bit storage units is the same as an order of lengths of the delay time of the write control signal of the first and second bit storage units.
    Type: Application
    Filed: February 10, 2015
    Publication date: August 20, 2015
    Inventors: Kazuhiro Saito, Hiroaki Kameyama, Kohichi Nakamura
  • Publication number: 20150229832
    Abstract: Provided is a photoelectric conversion apparatus including: a pixel array having pixels arranged in matrix; a pixel output line provided according to each column of the pixel array and transmitting a pixel signal output from a pixel of each column of the pixel array; a column signal processing unit provided according to each column of the pixel array and into which the pixel signal is input from the pixel output line, in which the column signal processing unit has a plurality of horizontal adding up or averaging units configured to add up or average the plurality of pixel signals based on the pixels of different columns of the pixel array; and a plurality of adding up or averaging modes with different numbers of columns subjected to adding up or averaging can be selected by selectively using one or a plurality of the plurality of horizontal adding up or averaging units.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 13, 2015
    Inventors: Tetsuya Itano, Kohichi Nakamura, Hideo Kobayashi
  • Publication number: 20150201144
    Abstract: A solid-state imaging apparatus includes: a pixels in a matrix for generating a pixel signal; and A/D converting units, corresponding to columns of the matrix, to convert the pixel signal into a n-bit digital value. The A/D converting units includes first storage units for storing the n-bit digital value one bit by one bit, and second storage units corresponding to the first storage units, to hold the digital value transferred from the first storage unit. In each of the columns of the plurality of pixels, arranged corresponding thereto are the first storage units and the second storage units form n-pairs. Each pair including the first storage unit and the second storage unit hold the digital value of the same bit. The n-pairs are arrayed in a matrix.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 16, 2015
    Inventors: Hideo Kobayashi, Kohichi Nakamura, Tetsuya Itano, Yasushi Matsuno
  • Patent number: 9083906
    Abstract: Provided is an A/D converter including an input terminal, a reference signal line for supplying a reference signal which changes temporally, a comparator, a correction capacitor connected to an inverting input terminal of the comparator; and an output circuit which outputs digital data corresponding to an analog signal input to the input terminal. In a first state in which a total voltage of a first analog signal and an offset voltage of the comparator is held in the correction capacitor, a second analog signal input to the input terminal is supplied to a non-inverting input terminal of the comparator, and the second analog signal or the total voltage is changed using the reference signal, thereby outputting, from the output circuit, digital data.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: July 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kohichi Nakamura, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito
  • Patent number: 9077918
    Abstract: A photoelectric conversion apparatus includes, on one substrate, a pixel driving unit and a signal processing unit that includes a digital circuit configured to execute signal processing. A first voltage and a second voltage different in value from the first voltage are supplied to the digital circuit of the pixel driving unit. A third voltage and a fourth voltage different in value from the third voltage are supplied to the digital circuit of the signal processing unit. A main portion of a first conductor that supplies the first voltage to the digital circuit of the pixel driving unit and a main portion of a second conductor that supplies the third voltage to the digital circuit of the signal processing unit are isolated from each other.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 7, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Kohichi Nakamura, Yu Maehashi, Koichiro Iwata
  • Publication number: 20150172581
    Abstract: First processing of causing a hold unit to hold a first signal from an amplification unit based on reset of the amplification unit, second processing of performing AD conversion of the held first signal and outputting a second signal obtained by superposing a signal based on charges generated in a photoelectric conversion unit of a first-row pixel on the first signal, third processing of performing an operation of performing AD conversion of the held second signal and an operation of resetting the amplification unit at least partly in parallel, and fourth processing of causing the hold unit to hold a fourth signal obtained by superposing a signal based on charges generated in the photoelectric conversion unit of a second-row pixel on a third signal from the amplification unit based on resetting of the amplification unit and is output from the amplification unit are performed.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 18, 2015
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata
  • Patent number: 9040887
    Abstract: Provided is an A/D converter including an input terminal, a reference signal line for supplying a reference signal which changes temporally, a comparator, a correction capacitor connected to an inverting input terminal of the comparator; and an output circuit which outputs digital data corresponding to an analog signal input to the input terminal. In a first state in which a total voltage of a first analog signal and an offset voltage of the comparator is held in the correction capacitor, a second analog signal input to the input terminal is supplied to a non-inverting input terminal of the comparator, and the second analog signal or the total voltage is changed using the reference signal, thereby outputting, from the output circuit, digital data.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: May 26, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kohichi Nakamura, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito
  • Publication number: 20150138411
    Abstract: An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.
    Type: Application
    Filed: October 17, 2014
    Publication date: May 21, 2015
    Inventors: Kohichi Nakamura, Hideo Kobayashi, Hiroki Hiyama, Kazuo Yamazaki
  • Patent number: 9029752
    Abstract: A solid-state imaging apparatus comprises a plurality of matrix pixels, a reference signal generator for generating a ramp signal, a counter for performing counting according to the ramp signal output, and an AD converter, arranged for each pixel column, for performing AD conversion by comparing a pixel signal from the pixel with the ramp signal. Further, the AD converter includes a comparator to which the pixel signal and the reference signal are input, a storage for storing the AD conversion result, and an slope converter, between the output terminal of the reference signal generator and the input terminal of the comparator, for changing a gradient of the ramp signal, so that the noise overlaid on the ramp signal changes depending on the gradient of the ramp signal. Thus, it is possible to prevent generation of a horizontal-line noise in the ramp signal.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura
  • Publication number: 20150122975
    Abstract: A solid-state imaging apparatus comprises a plurality of matrix pixels, a reference signal generator for generating a ramp signal, a counter for performing counting according to the ramp signal output, and an AD converter, arranged for each pixel column, for performing AD conversion by comparing a pixel signal from the pixel with the ramp signal. Further, the AD converter includes a comparator to which the pixel signal and the reference signal are input, a storage for storing the AD conversion result, and an slope converter, between the output terminal of the reference signal generator and the input terminal of the comparator, for changing a gradient of the ramp signal, so that the noise overlaid on the ramp signal changes depending on the gradient of the ramp signal. Thus, it is possible to prevent generation of a horizontal-line noise in the ramp signal.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 7, 2015
    Inventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura
  • Patent number: 8994866
    Abstract: A photoelectric conversion device includes a counter circuit configured to count a first clock signal to output a count signal thereof, a second clock signal generation unit configured to generate a second clock signal based on the first clock signal, and a clock synchronization unit configured to output a count start signal in synchronization with the second clock signal, wherein the counter circuit performs a counting operation in response to the count start signal synchronized with the second clock signal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 31, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kohichi Nakamura, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Yu Maehashi, Koichiro Iwata
  • Publication number: 20150042856
    Abstract: An imaging apparatus includes: a pixel configured to generate a signal through photoelectric conversion; a comparator configured to compare a signal generated by the pixel with a first reference signal that changes with time; and a control unit configured to change a change rate of the first reference signal with respect to time according to a comparison result of the comparator.
    Type: Application
    Filed: June 24, 2014
    Publication date: February 12, 2015
    Inventors: Kohichi Nakamura, Yasuji Ikeda