Patents by Inventor Kohichi Nakamura
Kohichi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150036032Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.Type: ApplicationFiled: July 30, 2014Publication date: February 5, 2015Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
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Patent number: 8928786Abstract: A solid-state imaging apparatus includes: a plurality of pixels arranged in a matrix; a plurality of amplifier circuits each arranged correspondingly to each of columns of the pixels, for amplifying a signal from the pixel; and a current source transistor whose source is supplied with a power source voltage and which supplies the amplifier circuit with a bias current. When the current source transistor is operating in the saturation region, the gate voltage of the current source transistor that is supplied from the bias line is sampled and held. The gate voltage of the current source transistor with respect to the power source voltage is controlled to the sampled voltage, thereby suppressing variation. This suppression can, in turn, suppress occurrence of line noise and a lateral smear due to difference of drop in voltage of a power source line concerning a column circuit on each row.Type: GrantFiled: September 12, 2012Date of Patent: January 6, 2015Assignee: Canon Kabushiki KaishaInventors: Koichiro Iwata, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura, Kazuhiro Saito
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Patent number: 8848079Abstract: A solid-state imaging device includes a plurality of pixels arranged in a matrix, a plurality of readout circuits provided in each column of the plurality of pixels arranged in a matrix, configured to read out for each column a signal of the plurality of pixels, a plurality of comparison units configured to compare a signal output from the plurality of readout circuits with a reference signal whose level changes with time, a counter configured to perform a count operation from when the level of the reference signal starts to change, first and second buffers each configured to buffer a count value of the counter, and a plurality of storing units connected to the plurality of comparison units, configured to store a count value of the counter when a magnitude relation between a signal output from the plurality of the readout circuits and the reference signal is inverted.Type: GrantFiled: September 27, 2012Date of Patent: September 30, 2014Assignee: Canon Kabushiki KaishaInventors: Tetsuya Itano, Hiroki Hiyama, Kazuhiro Saito, Kohichi Nakamura, Koichiro Iwata, Takeshi Akiyama, Kazuo Yamazaki, Daisuke Yoshida
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Patent number: 8836838Abstract: A solid-state imaging apparatus includes a plurality of pixels arranged two-dimensionally in a matrix, a reference signal generating circuit adapted to generate a ramp signal, a counter circuit adapted to perform a counting operation according to output of the ramp signal, comparators arranged on a column by column basis and adapted to compare signals read out of the pixels with the ramp signal, and memories arranged on a column by column basis and adapted to store digital data, wherein if output of the comparator is not changed during an AD conversion period, digital data of a predetermined value is stored in the memory. The solid-state imaging apparatus implements overflow handling using a simplified circuit configuration.Type: GrantFiled: August 16, 2012Date of Patent: September 16, 2014Assignee: Canon Kabushiki KaishaInventors: Kohichi Nakamura, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito
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Patent number: 8760213Abstract: A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.Type: GrantFiled: September 27, 2012Date of Patent: June 24, 2014Assignee: Canon Kabushiki KaishaInventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura
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Patent number: 8723099Abstract: An imaging apparatus includes a plurality of unit pixels arranged in a matrix and configured to generate a signal by photoelectric conversion, a plurality of pixel output lines connected to each column of the unit pixels, a plurality of column amplifiers configured to amplify a signal of the pixel output lines, and a driving circuit configured to generate a control signal of the column amplifiers. Each of the column amplifiers includes first and second input terminals, an output terminal, an input capacitance between the first and second input terminals, and a first switch between the second input and output terminals. The driving circuit is configured to generate the control signal so as to make a period for switching the first switch from a conductive state to a non-conductive state longer than a period for switching the first switch from the non-conductive state to the conductive state.Type: GrantFiled: September 10, 2012Date of Patent: May 13, 2014Assignee: Canon Kabushiki KaishaInventors: Tetsuya Itano, Hiroki Hiyama, Kazuhiro Saito, Kohichi Nakamura, Koichiro Iwata, Yu Maehashi, Takeshi Akiyama
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Patent number: 8711259Abstract: A solid-state imaging apparatus includes: an amplifier circuit configured to amplify a signal from pixel; and a reference signal generating circuit configured to generate a ramp signal, wherein feedback capacitor elements having the same structure are electrically connected to a capacitive feedback type amplifier of the amplifier circuit and to a capacitive feedback type amplifier of the reference signal generating circuit respectively, and a connecting configuration between an amplifier of the amplifier circuit and the feedback capacitor element and a connecting configuration between an amplifier of the reference signal generating circuit and the feedback capacitor element are the same.Type: GrantFiled: September 13, 2012Date of Patent: April 29, 2014Assignee: Canon Kabushiki KaishaInventors: Yu Maehashi, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Kohichi Nakamura
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Publication number: 20140098272Abstract: A photoelectric conversion device includes a plurality of pixels arranged in a plurality of columns, a plurality of comparators provided correspondingly to the respective columns, a reference signal generation unit configured to supply a reference signal to the plurality of comparators, a counter configured to generate a count signal that includes a plurality of bits in synchronization with a first clock signal, a synchronization unit configured to synchronize the plurality of bits with a second clock signal to generate a synchronized count signal and to output the generated synchronized count signal, and a plurality of memories provided correspondingly to the respective comparators, the memories each being configured to store the synchronized count signal in response to a change in an output of a corresponding one of the comparators.Type: ApplicationFiled: October 1, 2013Publication date: April 10, 2014Inventors: Kohichi Nakamura, Koichiro Iwata, Kazuhiro Saito, Takeshi Akiyama, Tetsuya Itano, Hiroki Hiyama, Takashi Muto
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Patent number: 8692920Abstract: In an A/D converter, a first analog signal which is input to an input terminal in a state in which the input terminal and a reference voltage line are connected via a first capacitor is converted into digital data when a reference signal is supplied to the reference signal line in a state in which the reference signal line and a first input terminal of a comparator are connected via the first capacitor. A second analog signal which is input to the input terminal in a state in which the input terminal and the reference voltage line are connected via a second capacitor is converted into digital data when the reference signal is supplied to the reference signal line in a state in which the reference signal line and the first input terminal of the comparator are connected via the second capacitor.Type: GrantFiled: August 9, 2012Date of Patent: April 8, 2014Assignee: Canon Kabushiki KaishaInventors: Hiroki Hiyama, Kohichi Nakamura, Kazuhiro Saito, Tetsuya Itano
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Publication number: 20140092286Abstract: A photoelectric conversion device includes a pixel array including a plurality of pixels arranged in a matrix, a plurality of blocks including a plurality of pairs, each of the pairs including a comparator provided correspondingly with a column in the pixel array and a memory provided correspondingly with the comparator, and a block information supply unit configured to supply block information which indicates a location of a block, to the plurality of memories included in the blocks.Type: ApplicationFiled: September 30, 2013Publication date: April 3, 2014Inventors: Hiroki Hiyama, Kohichi Nakamura, Kazuo Yamazaki, Kazuhiro Saito
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Publication number: 20140043511Abstract: A solid-state imaging apparatus includes: a plurality of first unit pixels configured to generate a signal by a photoelectric conversion; a first output line connected to the plurality of first unit pixels; and a first amplifier configured to amplify a signal from the first output line, wherein the first amplifier includes an operational amplifier (401), an initializing switch (404) having one terminal connected to an output terminal of the operational amplifier, and an offset adjusting unit (402) connected between the other terminal of the initializing switch and an input terminal of the operational amplifier, and the offset adjusting unit has a transistor having a source and a drain connected to each other.Type: ApplicationFiled: July 30, 2013Publication date: February 13, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Koichiro Iwata, Kazuhiro Saito, Kohichi Nakamura, Takeshi Akiyama
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Patent number: 8598901Abstract: A system includes: a plurality of pixels arranged in a matrix; a reference signal generating unit for generating a ramp signal; A/D converters each arranged correspondingly to each of columns to A/D-convert a signal from the pixel; a counter that performs a count operation according to an output of the ramp signal, and supplies the count signal through the count signal line to the A/D converter; and a counter test circuit that is provided independently from the A/D converter, and tests the counter, based on a matching of the expected value of the count signal with the count signal supplied through the count signal line from the counter. This configuration allows the count signal to be checked concurrently with imaging of an object.Type: GrantFiled: September 21, 2012Date of Patent: December 3, 2013Assignee: Canon Kabushiki KaishaInventors: Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Yu Maehashi, Koichiro Iwata, Kohichi Nakamura
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Publication number: 20130235241Abstract: A solid-state imaging apparatus that shortens a time for reading out pixel signals of all pixels and improves the aperture ratio of pixels is provided. The solid-state imaging apparatus includes a plurality of pixels (3) arranged in a matrix along a plurality of rows and columns, in which each of the pixels includes a photoelectric conversion element and a color filter; a plurality of buffers (2) arranged with each one corresponding to a plurality of pixels; and a plurality of vertical output lines (1) arranged such that two or more of the vertical output lines (1) are arranged correspondingly to one of the columns of the pixels; in which an input node of each of the buffers is connected commonly to a plurality of pixels having color filters of different colors, and output nodes of the plurality of buffers are connected alternately to a plurality of vertical output lines.Type: ApplicationFiled: April 26, 2013Publication date: September 12, 2013Applicant: Canon Kabushiki KaishaInventors: Kohichi Nakamura, Hiroki Hiyama
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Patent number: 8497885Abstract: A display apparatus includes a matrix of light emitting elements, a plurality of drive circuits provided for driving the light emitting elements, a plurality of scanning lines to which a scanning signal is applied to select the drive circuits on a row basis, a plurality of control lines to which a light-emission control signal is applied to determine an emission period of the light emitting elements, and a plurality of data lines to which image signals are applied to define brightness of the light emitting elements on a column basis. The scanning signal is sequentially applied to the scanning lines in a field so that the image signals of the data lines are programmed in the drive circuits, and the light-emission control signal is sequentially applied to the control lines to make the light emitting elements emit light with brightness corresponding to the image signal programmed to the drive circuit.Type: GrantFiled: August 20, 2008Date of Patent: July 30, 2013Assignee: Canon Kabushiki KarshaInventors: Kouji Ikeda, Kohichi Nakamura, Masami Iseki
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Patent number: 8451360Abstract: A solid-state imaging apparatus that shortens a time for reading out pixel signals of all pixels and improves the aperture ratio of pixels is provided. The solid-state imaging apparatus includes a plurality of pixels (3) arranged in a matrix along a plurality of rows and columns, in which each of the pixels includes a photoelectric conversion element and a color filter; a plurality of buffers (2) arranged with each one corresponding to a plurality of pixels; and a plurality of vertical output lines (1) arranged such that two or more of the vertical output lines (1) are arranged correspondingly to one of the columns of the pixels; in which an input node of each of the buffers is connected commonly to a plurality of pixels having color filters of different colors, and output nodes of the plurality of buffers are connected alternately to a plurality of vertical output lines.Type: GrantFiled: April 26, 2010Date of Patent: May 28, 2013Assignee: Canon Kabushiki KaishaInventors: Kohichi Nakamura, Hiroki Hiyama
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Publication number: 20130087685Abstract: An imaging apparatus includes a plurality of unit pixels arranged in a matrix and configured to generate a signal by photoelectric conversion, a plurality of pixel output lines connected to each column of the unit pixels, a plurality of column amplifiers configured to amplify a signal of the pixel output lines, and a driving circuit configured to generate a control signal of the column amplifiers. Each of the column amplifiers includes first and second input terminals, an output terminal, an input capacitance between the first and second input terminals, and a first switch between the second input and output terminals. The driving circuit is configured to generate the control signal so as to make a period for switching the first switch from a conductive state to a non-conductive state longer than a period for switching the first switch from the non-conductive state to the conductive state.Type: ApplicationFiled: September 10, 2012Publication date: April 11, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Tetsuya Itano, Hiroki Hiyama, Kazuhiro Saito, Kohichi Nakamura, Koichiro Iwata, Yu Maehashi, Takeshi Akiyama
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Publication number: 20130088627Abstract: A photoelectric conversion device includes a counter circuit configured to count a first clock signal to output a count signal thereof, a second clock signal generation unit configured to generate a second clock signal based on the first clock signal, and a clock synchronization unit configured to output a count start signal in synchronization with the second clock signal, wherein the counter circuit performs a counting operation in response to the count start signal synchronized with the second clock signal.Type: ApplicationFiled: September 12, 2012Publication date: April 11, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Kohichi Nakamura, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Yu Machashi, Koichiro Iwata
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Publication number: 20130088292Abstract: A solid-state imaging apparatus includes: an amplifier circuit configured to amplify a signal from pixel; and a reference signal generating circuit configured to generate a ramp signal, wherein feedback capacitor elements having the same structure are electrically connected to a capacitive feedback type amplifier of the amplifier circuit and to a capacitive feedback type amplifier of the reference signal generating circuit respectively, and a connecting configuration between an amplifier of the amplifier circuit and the feedback capacitor element and a connecting configuration between an amplifier of the reference signal generating circuit and the feedback capacitor element are the same.Type: ApplicationFiled: September 13, 2012Publication date: April 11, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Yu Maehashi, Hiroki Hiyama, Tetsuya Itano, Kazuhiro Saito, Kohichi Nakamura
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Publication number: 20130087686Abstract: A solid-state imaging apparatus includes a plurality of pixels arrayed in a matrix, and configured to generate signals by photoelectric conversion; a plurality of read-out circuits disposed on each column of the plurality of pixels arrayed in a matrix pattern, and configured to read out the signals from the plurality of pixels; a plurality of comparison units configured to compare the signals output from the plurality of read-out circuits with a reference signal whose level changes with time; a counter configured to count a clock signal after the level of the reference signal starts a change; a storage unit configured, when a magnitude relationship between the signals output from the plurality of the read-out circuits and the reference signal is reversed; and a reset unit configured to reset the count value stored in the storage unit.Type: ApplicationFiled: September 11, 2012Publication date: April 11, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Tetsuya Itano, Hiroki Hiyama, Kazuhiro Saito, Kohichi Nakamura, Yu Maehashi
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Publication number: 20130088625Abstract: A solid-state imaging apparatus includes: a plurality of pixels arranged in a matrix; a plurality of amplifier circuits each arranged correspondingly to each of columns of the pixels, for amplifying a signal from the pixel; and a current source transistor whose source is supplied with a power source voltage and which supplies the amplifier circuit with a bias current. When the current source transistor is operating in the saturation region, the gate voltage of the current source transistor that is supplied from the bias line is sampled and held. The gate voltage of the current source transistor with respect to the power source voltage is controlled to the sampled voltage, thereby suppressing variation. This suppression can, in turn, suppress occurrence of line noise and a lateral smear due to difference of drop in voltage of a power source line concerning a column circuit on each row.Type: ApplicationFiled: September 12, 2012Publication date: April 11, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Koichiro Iwata, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura, Kazuhiro Saito