Abstract: According to one embodiment, in a storage device, a selection circuit selects one mapping rule from a plurality of mapping rules in which each of bit labels having a bit length of (n+1) or more is mapped to n M-ary symbols, when M is defined as an integer of 3 or more and n is defined as an integer of or more. A first conversion circuit converts a data block in data into an M-ary symbol sequence using the selected one mapping rule. A second conversion circuit converts the converted M-ary symbol sequence into an M-step pulse width signal. The recording medium records the converted M-step pulse width signal. A readback circuit equalizes the signal read from the recording medium to the M-ary symbol sequence and restores the data.

Abstract: according to one embodiment, in a storage device, a selection circuit selects one mapping rule from a plurality of mapping rules in which each of bit labels having a bit length of (n+1) or more is mapped to n M-ary symbols, when M is defined as an integer of 3 or more and n is defined as an integer of or more. A first conversion circuit converts a data block in data into an M-ary symbol sequence using the selected one mapping rule. A second conversion circuit converts the converted M-ary symbol sequence into an M-step pulse width signal. The recording medium records the converted M-step pulse width signal. A readback circuit equalizes the signal read from the recording medium to the M-ary symbol sequence and restores the data.

Abstract: According to one embodiment, there is provided a storage device including a controller circuit and a storage medium. The controller circuit includes a first conversion circuit and a second conversion circuit. The first conversion circuit converts data into M-ary symbols where M is an integer of 3 or more. The second conversion circuit converts respective ones of the converted n samples of M-ary symbols into signals with L-patterned pulse width where n is an integer of 2 or more. The storage medium stores the converted n samples of signals with L-patterned pulse width. The controller circuit further includes an equalization circuit that equalizes signals read from the storage medium into the n samples of M-ary symbols.

Abstract: According to one embodiment, there is provided a storage device including a controller circuit and a storage medium. The controller circuit includes a first conversion circuit and a second conversion circuit. The first conversion circuit converts data into M-ary symbols where M is an integer of 3 or more. The second conversion circuit converts respective ones of the converted n samples of M-ary symbols into signals with L-patterned pulse width where n is an integer of 2 or more. The storage medium stores the converted n samples of signals with L-patterned pulse width. The controller circuit further includes an equalization circuit that equalizes signals read from the storage medium into the n samples of M-ary symbols.

Abstract: A memory system according to an embodiment includes a plurality of magnetic nanowires, a read unit that reads data from the magnetic nanowires, a shift control unit that shifts domain walls in the magnetic nanowires, and a read control unit. The read control unit is configured to control the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, and when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, determines a misalignment in the data and correct the data based on the misalignment.

Abstract: According to one embodiment, there is provided a storage device including a data converter, a recording medium, and an equalizer. The data converter converts data into sets of n number of four-ary symbols according to mapping rules in which 22n-1 or fewer types of bit labels are mapped onto the n number of four-ary symbols, where n is an integer of two or greater. Onto the recording medium, the converted n number of four-ary symbols are recorded in the form of a signal of one level among four levels. The equalizer equalizes a signal read from the recording medium into sets of the n number of four-ary symbols.

Abstract: A memory system according to an embodiment includes: a plurality of magnetic nanowires; a read unit configured to read data from the magnetic nanowires; a shift control unit configured to shift domain walls in the magnetic nanowires; and a read control unit configured to cause the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, determine a misalignment in the data when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, and correct the stored data based on the determined misalignment.

Abstract: According to one embodiment, there is provided a memory system including a first generating unit, a buffer unit, a decoding unit, and an update unit. The first generating unit generates logarithm likelihood ratios for plural pieces of data read from a plurality of memory cells. The buffer unit stores the logarithm likelihood ratios. The decoding unit performs first error correction decoding process on the logarithm likelihood ratios, and estimates a logarithm likelihood ratio of data corresponding to an error memory cell among the plural pieces of read data. The update unit updates the logarithm likelihood ratios stored in the buffer unit using the estimated logarithm likelihood ratio.

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.

Abstract: According to one embodiment, a magnetic recording and reproducing device includes magnetic recording medium and a magnetic head. The magnetic recording medium includes a first surface. A plurality of bits is provided in the first surface. Each of the bits has a direction of magnetization corresponding to recorded information. The magnetic head includes a reproducing unit. The reproducing unit senses the direction of magnetization. The reproducing unit includes a first shield, a second shield, a first magnetic layer, a second magnetic layer, a third magnetic layer, a fourth magnetic layer, an intermediate layer, a first nonmagnetic layer, and a second nonmagnetic layer. The first and the second nonmagnetic layers include at least one selected from ruthenium, copper, and tantalum. A distance between the first shield and the second shield is not less than 3 times and not more than 7 times a length of each of the bits.

Abstract: According to one embodiment, there is provided a memory controller that controls nonvolatile memory of K bits/cell, first and second bits of the K bits corresponding to first and second pages, the memory controller including an encoder configured to encode unit data to write in a first page to generate a parity; and a decoder configured to perform an error correction process using the readout unit data and the parity; where readout of the first page is carried out using 2K?1 first voltage values, readout of the second page is carried out using a second voltage value, which is less in number than 2K?1, and a bit value of the second page is selected based on a bit value of the first page of after the error correction.

Abstract: According to one embodiment, a magnetic recording and reproducing device includes magnetic recording medium and a magnetic head. The magnetic recording medium includes a first surface. A plurality of bits is provided in the first surface. Each of the bits has a direction of magnetization corresponding to recorded information. The magnetic head includes a reproducing unit. The reproducing unit senses the direction of magnetization. The reproducing unit includes a first shield, a second shield, a first magnetic layer, a second magnetic layer, a third magnetic layer, a fourth magnetic layer, an intermediate layer, a first nonmagnetic layer, and a second nonmagnetic layer. The first and the second nonmagnetic layers include at least one selected from ruthenium, copper, and tantalum. A distance between the first shield and the second shield is not less than 3 times and not more than 7 times a length of each of the bits.

Abstract: According to one embodiment, an equalizer is configured to obtain a noise included in a first correction signal by using a noise component of a first track and a noise interference component from a second track. The equalizer is configured to correct the first correction signal by using the obtained noise. The equalizer is configured to equalize the corrected first correction signal. The noise component of the first track is calculated based on a noise component of the first track at a first timing and a noise component of the first track at a second timing earlier than the first timing. The noise interference component from the second track is calculated based on a noise interference component from the second track at the first timing and a noise interference component from the second track at the second timing. The decoder is configured to decode the equalized first correction signal.

Abstract: According to one embodiment, a memory controller comprises an encoding unit that encodes first unit data and second unit data to generate a first codeword and a second codeword; a rearranging unit that extracts a first bit string in specific bit positions from each of the first and second codewords to generate first page data and to generate second page data containing the remaining bit strings other than the first bit strings respectively in the first and second codewords; and a write control unit that writes the first page data and the second page data respectively into a first page and a second page of a nonvolatile memory.

Abstract: According to one embodiment, a storage device includes a data conversion unit that coverts user data of n bits, into m three-ary symbols, a recording medium that records the symbols as a signal of any one of three levels corresponding to values of the symbols, and a Viterbi equalizer that performs equalization of the m symbols simultaneously based on a signal read from the recording medium while setting the number of states as a power of 3 and using a trellis diagram having 2n branches, and calculates 2n likelihoods.

Abstract: According to one embodiment, switching takes place between a first control in which a first read head is assigned as a master head for reading data from a magnetic disk on which a sequential write direction is reversed at a switching position where a skew angle of a write head becomes 0 and between an outer periphery and an inner periphery in shingled write recording, and a second read head is assigned as a slave head for reducing inter-track interference during reading of the data and noise by virtue of an effect of waveform averaging with respect to the master head, and a second control in which the second read head is assigned as the master head and the first read head is assigned as the slave head.

Abstract: According to one embodiment, a recording and reproducing apparatus includes a first masking unit configured to apply first bit masking to error correction code (ECC) encoded data using a bit sequence for masking, to generate a masked bit sequence to be recorded on a medium, and a de-masking unit configured to apply de-masking, using the bit sequence for masking, to a sequence of decision values based on a signal read from the medium to generate a sequence of de-masked decision values to be ECC decoded. The bit sequence for masking comprises an iteration of a fixed bit sequence of N (>1) bits. The bit de-masking is an inverse process corresponding to the first bit masking.

Abstract: According to one embodiment, there is provided a controller including an interference cancelling module, a boosting module, and a decoding module. The interference cancelling module generates a first correction signal by cancelling an interference component from an adjacent track in a signal read from a target track of a disk medium. The boosting module generates a second correction signal by boosting a low frequency component of a signal corresponding to the first correction signal. The decoding module decodes a signal based on the second correction signal.

Abstract: According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.