Patents by Inventor Koichi Hirano

Koichi Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8435842
    Abstract: A method for manufacturing a flexible semiconductor device comprises (i) forming an insulating film on the upper surface of a resin film, (ii) forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one of the stepsof the above steps (i) to (iv) is carried out by a printing method. With this manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa
  • Publication number: 20130032797
    Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.
    Type: Application
    Filed: December 19, 2011
    Publication date: February 7, 2013
    Inventors: Koichi Hirano, Shingo Komatsu, Yasuteru Saito, Naoki Ike
  • Patent number: 8367488
    Abstract: A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano
  • Patent number: 8343822
    Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa, Takashi Ichiryu, Takeshi Suzuki
  • Patent number: 8344264
    Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Yutaka Kumano, Hideki Iwaki, Tetsuyoshi Ogura, Shingo Komatsu, Koichi Hirano
  • Patent number: 8324623
    Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: December 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani
  • Publication number: 20120286264
    Abstract: There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (a) preparing a metal foil having a concave portion; (b) forming a gate insulating film on a bottom face of the concave portion of the metal foil; (c) forming a semiconductor layer above the bottom face of the concave portion via the gate insulating film while making use of the concave portion as a bank member; and (d) forming a source electrode and a drain electrode such that they make contact with the semiconductor layer.
    Type: Application
    Filed: April 22, 2011
    Publication date: November 15, 2012
    Inventors: Takeshi Suzuki, Seiichi Nakatani, Koichi Hirano
  • Publication number: 20120280229
    Abstract: There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (A) providing a metal foil; (B) forming an insulating layer on the metal foil, the insulating layer having a portion serving as a gate insulating film; (C) forming a supporting substrate on the insulating layer; (D) etching away a part of the metal foil to form a source electrode and a drain electrode therefrom; (E) forming a semiconductor layer in a clearance portion located between the source electrode and the drain electrode by making use of the source and drain electrodes as a bank member; and (F) forming a resin film layer over the insulating layer such that the resin film layer covers the semiconductor layer, the source electrode and the drain electrode. In the step (F), a part of the resin film layer interfits with the clearance portion located between the source and drain electrodes.
    Type: Application
    Filed: April 22, 2011
    Publication date: November 8, 2012
    Inventors: Takeshi Suzuki, Koichi Hirano
  • Publication number: 20120181543
    Abstract: Disclosed are a flexible semiconductor device and manufacturing method therefor whereby the capacitances of capacitor parts of semiconductor elements and the like can be increased while decreasing parasitic capacitances that arise between multilevel interconnections. The disclosed flexible semiconductor device is provided with an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element comprises: a semiconductor layer formed on the top surface of the insulating film; a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer; and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer.
    Type: Application
    Filed: April 14, 2011
    Publication date: July 19, 2012
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano
  • Publication number: 20120113500
    Abstract: Provided is an electronic paper that permits a high-quality, large area to be easily created. Also provided is a method for producing the electronic paper. The electronic paper comprises: a first substrate upon which first electrodes are formed and a second substrate upon which second electrodes are formed, said first substrate and second substrate disposed so as to face each other; and a plurality of cell spaces constituting pixels between said first substrate and second substrate. The first substrate comprises a plurality of first sheet members, each having a first electrode formed thereon. By disposing a cover substrate on said first sheet members, each with a partition wall therebetween, a plurality of subsheet formations comprising the plurality of cell spaces partitioned by the partition walls are formed, and the first electrodes are connected in between adjacent subsheet formations.
    Type: Application
    Filed: April 14, 2011
    Publication date: May 10, 2012
    Inventors: Koichi Hirano, Masami Nakagawa, Seiichi Nakatani
  • Publication number: 20120001173
    Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The resin film comprises an opening formed by a laser irradiation therein, and also an electroconductive member which is in contact with the surface of the semiconductor structure portion is disposed within the opening of the resin film.
    Type: Application
    Filed: February 2, 2010
    Publication date: January 5, 2012
    Inventors: Takeshi Suzuki, Kenichi Hotehama, Seiichi Nakatani, Koichi Hirano, Tatsuo Ogawa
  • Patent number: 8063486
    Abstract: A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Tsukasa Shiraishi, Seiichi Nakatani, Tatsuo Ogawa
  • Publication number: 20110180900
    Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Koichi HIRANO, Tetsuyosyi Ogura, Seiichi Nakatani
  • Patent number: 7981528
    Abstract: A water-repelling layer is formed on a resin film, and a stripe pattern region is formed so as to be positioned within a surface region of the water-repelling layer and so as to be relatively hydrophilic with respect to water repellency of the water-repelling layer. A magnetic stripe pattern is formed of needle-shaped magnetic grains oriented and aggregated in the stripe pattern region. The needle-shaped magnetic grains are arranged in a desirable state in a predetermined stripe pattern, with a high magnetic permeability and a magnetic sheet with stripe-arranged magnetic grains that is thin and flexible is obtained.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Ichiryu, Koichi Hirano
  • Patent number: 7977741
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20110162578
    Abstract: [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals.
    Type: Application
    Filed: March 11, 2011
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Yoshihiro Tomita, Seiichi Nakatani
  • Publication number: 20110133137
    Abstract: A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Inventors: Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Yoshihiro Tomita
  • Publication number: 20110121298
    Abstract: A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
    Type: Application
    Filed: February 5, 2010
    Publication date: May 26, 2011
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano
  • Patent number: 7943518
    Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: May 17, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani
  • Patent number: 7927997
    Abstract: To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: April 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Yoshihiro Tomita, Seiichi Nakatani