Patents by Inventor Koichi Hirano

Koichi Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7910403
    Abstract: A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Yoshihiro Tomita
  • Publication number: 20110049598
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Application
    Filed: November 4, 2010
    Publication date: March 3, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Koichi HIRANO, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20110042677
    Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprises a metal layer comprising a gate electrode, a source electrode and a drain electrode; a metal oxide film made from a metal which constitutes the metal layer and formed over a surface region of the metal layer; and a semiconductor layer formed above the gate electrode via the metal oxide film. In the flexible semiconductor device, uncovered portions, each of which is not covered with the metal oxide film, are locally formed in the surface region of the metal layer; and also electrical connections are formed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer via the uncovered portions.
    Type: Application
    Filed: November 13, 2009
    Publication date: February 24, 2011
    Inventors: Takeshi Suzuki, Kenichi Hotehama, Koichi Hirano, Seiichi Nakatani
  • Patent number: 7888789
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Patent number: 7851281
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20100283054
    Abstract: There is provided a method for manufacturing a flexible semiconductor device characterized by comprising (i) a step of forming an insulating film on the upper surface of metal foil, (ii) a step of forming an extraction electrode pattern on the upper surface of the metal foil, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the extraction electrode pattern, (iv) a step of forming a sealing resin layer on the upper surface of the metal foil in such a manner that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) a step of forming electrodes by etching the metal foil, wherein the metal foil is used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v).
    Type: Application
    Filed: July 30, 2009
    Publication date: November 11, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa, Takashi Ichiryu, Takeshi Suzuki
  • Publication number: 20100276691
    Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 4, 2010
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano, Yoshihisa Yamashita, Shingo Komatsu
  • Publication number: 20100261321
    Abstract: There is provided a method for manufacturing a flexible semiconductor device. The manufacturing method is characterized by comprising (i) a step of forming an insulating film on the upper surface of a resin film, (ii) a step of forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) a step of forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one forming step among the above (i) to (iv) is carried out by a printing method. In the manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.
    Type: Application
    Filed: July 30, 2009
    Publication date: October 14, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa
  • Patent number: 7801491
    Abstract: A wireless communication system includes: a main antenna for radiating an electromagnetic wave to wireless IC chips; a reflecting plate for reflecting the electromagnetic wave from the main antenna to the wireless IC chips; and a control unit which supports the wireless IC chips. The control unit causes a difference between the receiving electromagnetic wave levels of a direct wave from the main antenna and a reflected wave from the reflecting plate received by the antenna of the wireless IC chip.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: September 21, 2010
    Assignee: NEC Corporation
    Inventors: Shigeru Hatakeyama, Shigeru Yamazaki, Hiroki Murayama, Koichi Hirano
  • Patent number: 7754529
    Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomita, Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Toshio Fujii
  • Patent number: 7748110
    Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Asahi, Seiji Karashima, Takashi Ichiryu, Seiichi Nakatani, Tousaku Nishiyama, Koichi Hirano, Osamu Shibata, Takeshi Nakayama, Yoshiyuki Saito
  • Publication number: 20100164061
    Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.
    Type: Application
    Filed: August 24, 2007
    Publication date: July 1, 2010
    Inventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani
  • Patent number: 7726545
    Abstract: A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Seiji Karashima, Yoshihiro Tomita, Koichi Hirano, Toshio Fujii
  • Publication number: 20100012936
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 21, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7641412
    Abstract: A ball-point pen, wherein a cover member (6) is fitted to a joint member (3) connecting a writing tip (1) rotatably supporting a writing ball (2) at the tip thereof to an ink storage tube. When the cover member (6) is fitted to the joint member (3) along the outer peripheral surface thereof, a part of the cover member does not come within 0.2 mm (within the range of the chain double-dashed line) from around the writing tip. Thus, even if the accuracies of parts and assembly machines are dispersed, a problem with an existing ball-point pen wherein a cover member is brought into contact with a writing tip and the writing tip is damaged in an assembly step can be avoided.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: January 5, 2010
    Assignee: Mitsubishi Pencil Co., Ltd.
    Inventor: Koichi Hirano
  • Publication number: 20090321124
    Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 31, 2009
    Inventors: Yutaka KUMANO, Hideki IWAKI, Tetsuyoshi OGURA, Shingo KOMATSU, Koichi HIRANO
  • Publication number: 20090203169
    Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically.
    Type: Application
    Filed: February 2, 2006
    Publication date: August 13, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Tomita, Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Toshio Fujii
  • Publication number: 20090085227
    Abstract: A flip chip mounting body in which a circuit substrate having a plurality of connection terminals and an electronic part (semiconductor chip) having a plurality of electrode terminals are aligned face to face with each other, with a resin composition composed of solder powder, a resin and a convection additive being sandwiched in between, while a means such as spacers is interposed in between so as to provide a uniform gap between the two parts, or the electronic part (semiconductor chip) is placed inside a plate-shaped member having two or more protruding portions, so that the solder powder is allowed to move through boiling of the convection additive and to be self-aggregated to form a solder layer, thereby electrically connecting the connection terminals and the electrode terminals; and a mounting method for such a mounting body.
    Type: Application
    Filed: May 9, 2006
    Publication date: April 2, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tsukasa Shiraishi, Seiichi Nakatani, Seiji Karashima, Koichi Hirano, Takashi Kitae, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7400512
    Abstract: A module incorporating a capacitor, the module including a circuit board and a layer incorporating a capacitor, wherein the circuit board includes a wiring layer and a via contact for providing electrical conductivity to a cathode and an anode of the capacitor. The layer incorporating the capacitor includes a ferromagnetic layer integrated with at least a portion of a surface of the capacitor, and in the circuit board or the layer incorporating the capacitor a coil is wound around the capacitor, or an inductor component is disposed in parallel with the capacitor. Accordingly, a module incorporating a capacitor in which miniaturization, a higher density and a reduced thickness have been achieved, as well as a method for producing the module and a capacitor used for the module, are provided.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Tsunenori Yoshida, Seiichi Nakatani
  • Publication number: 20080165518
    Abstract: A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow.
    Type: Application
    Filed: March 13, 2006
    Publication date: July 10, 2008
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Seiji Karashima, Yoshihiro Tomita, Koichi Hirano, Toshio Fujii