Abstract: One object is to provide a polishing machine and a polishing method capable of improving a processing accuracy on the surface of an object. A method of polishing an object is provided. Such a method comprises: a first step of polishing an object by moving the object and a first polishing pad having a smaller dimension than that of the object relative to each other while the first polishing pad is made to contact the object, a second step of polishing the object, after the first step of polishing, by moving the object and a second polishing pad having a larger dimension than that of the object relative to each other while the second polishing pad is made to contact the object, and a step of detecting the state of the surface of the object before the first step of polishing.

Abstract: According to one embodiment of the present disclosure, provided is a method of calibrating a relationship among a pressure command value, a pressure in an air-bag, and a pressure read value of the air-bag in a substrate polishing apparatus, the substrate polishing apparatus including: a polishing table; the air-bag configured to press a substrate against the polishing table, the pressure for pressing the substrate being variable; and a pressure control unit configured to control the pressure in the air-bag in accordance with the pressure command value inputted to the pressure control unit, and read the pressure in the air-bag.

Abstract: The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

Abstract: According to one embodiment, a semiconductor device includes: an inverter gate circuit which inverts and outputs a logic level of an input signal, the inverter gate circuit includes a constant current source and a switch unit which are connected in series between a first power supply wiring and a second power supply wiring, and, according to the control signal, the switch unit switches real values of a gate length and a gate width of a switch transistor configured by a transistor to which a current outputted from the constant current source is applied among a plurality of transistors.

Abstract: According to one embodiment, a semiconductor device includes: an inverter gate circuit which inverts and outputs a logic level of an input signal, the inverter gate circuit includes a constant current source and a switch unit which are connected in series between a first power supply wiring and a second power supply wiring, and, according to the control signal, the switch unit switches real values of a gate length and a gate width of a switch transistor configured by a transistor to which a current outputted from the constant current source is applied among a plurality of transistors.

Abstract: To provide a receiver, a communication device, and a communication method capable of restoring a signal transmitted via a non-contact transmission channel with high accuracy. A communication device has a transmission circuit that converts an input signal into a pulse, a non-contact transmission channel that has a primary side coil and a secondary side coil and transmits the pulse from the transmission circuit in a non-contact manner, a restoration circuit that restores the input signal on the basis of a reception signal corresponding to the pulse transmitted via the non-contact transmission channel, an initialization unit that initializes an output of the non-contact transmission channel, and an initialization control unit that outputs a control signal of controlling the initialization unit on the basis of the reception signal corresponding to the pulse received via the non-contact transmission channel.

Abstract: An adjustment apparatus capable of adjusting various types of processing units of a substrate processing apparatus within a shorter period of time is disclosed. The adjustment apparatus includes a main operation device configured to manipulate the processing units and adjust the designated operations, terminal operation devices configured to manipulate the processing units and adjust the designated operations, a network that connects the processing units and the main operation device to each other; and connecting devices configured to connect the terminal operation devices to the network and disconnect the terminal operation devices from the network. Each of the terminal operation devices is configured to be able to manipulate at least one of the processing units.

Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.

Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.

Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.

Abstract: A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.

Abstract: A transmitter circuit has transistors each of which is provided between an other end of a primary coil to whose one end a power supply voltage is supplied and either of a power supply voltage terminal and a ground voltage terminal, respectively, and a control circuit for, when causing no current to flow through the primary coil, turning on the one transistor and turning off the other transistor.

Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.

Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.

Abstract: An object of the present invention is to provide a plastic ampule capable of suppressing volatilization and scattering of a drug solution and elution of plastic compounding ingredients into the drug solution, as well as suppressing whisker formation and deformation and damage of an opening when the plastic ampule is opened. A plastic ampule 10 according to the present invention includes a drug solution storage part 11 for storing a drug solution, a drug solution discharge tube 12 in communication with the drug solution storage part 11 and extending toward one side, and a top part 13 closing an end at the one side of the drug solution discharge tube 12, and the drug solution discharge tube 12 includes a fragile part 14 formed to have a thin thickness along a circumferential direction.

Abstract: A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period.

Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.

Abstract: A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.

Abstract: Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit.

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first dire