Abstract: A polishing apparatus includes a loading section (14) for placing therein a cassette (12) in which a plurality of polishing objects are housed; a first polishing line (20) and a second polishing line (30) for polishing a polishing object; a cleaning line (40) having cleaning machines (42a, 42b, 42c, 42d) for cleaning the polishing object after polishing and a transport unit (44) for transporting the polishing object; a transport mechanism (50) for transporting the polishing object between the loading section (14), the polishing lines (20, 30) and the cleaning line (40); and a control section for controlling the polishing lines (20, 30), the cleaning line (40) and the transport mechanism (50).

Abstract: The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.

Abstract: The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption.

Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.

Abstract: A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array.

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first dire

Abstract: A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period.

Abstract: A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep.

Abstract: A personal service support method for assisting an inquiry about a user operation in a virtual world, a computer program product, and a system for the same. The method includes: storing a dialog between a user and an agent; connecting the dialog in a list structure with another dialog in the list structure to produce a created dialog in a branch tree structure; and recording the created dialog in the branch tree structure. The computer program product tangibly embodies instructions which when implemented causes a computer to execute the steps of the method. The system includes: a dialog storage unit which stores a dialog between a user and an agent; and a dialog creating unit which connects the dialog in the list structure with another dialog in the list structure to create a dialog in a branch tree structure.

Abstract: Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.

Abstract: A prime number generating device is provided that includes a computation unit capable of performing at least addition and division on data of a predetermined number of bits or less; a prime number candidate data generating unit that generates prime number candidate data with a larger number of bits than the predetermined number of bits; a partitioned prime number candidate data generating unit that generates a plurality of partitioned prime number candidate data elements by partitioning the prime number candidate data; and a determination data generating unit that generates determination data for determining whether or not the prime number candidate expressed by the prime number candidate data is a composite number by using the computation unit to add together the respective plurality of partitioned prime number candidate data elements.

Abstract: An object of the present invention is to provide a plastic ampule capable of suppressing volatilization and scattering of a drug solution and elution of plastic compounding ingredients into the drug solution, as well as suppressing whisker formation and deformation and damage of an opening when the plastic ampule is opened. A plastic ampule 10 according to the present invention includes a drug solution storage part 11 for storing a drug solution, a drug solution discharge tube 12 in communication with the drug solution storage part 11 and extending toward one side, and a top part 13 closing an end at the one side of the drug solution discharge tube 12, and the drug solution discharge tube 12 includes a fragile part 14 formed to have a thin thickness along a circumferential direction.

Abstract: A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array.

Abstract: The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.

Abstract: Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit.

Abstract: A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained.

Abstract: A semiconductor device is provided with an SRAM cell unit. The SRAM cell unit is provided with a data storing section composed of a pair of drive transistors and a pair of load transistors; a data write section composed of a pair of access transistors; and a data read section composed of an access transistor and a drive transistor. Each of the transistors is provided with a semiconductor layer protruding from a base plane; a gate electrode extending on the both facing side planes over the semiconductor layer from above; a gate insulating film between a gate electrode and a semiconductor layer; and a source/drain region. Each semiconductor layer is arranged to have its longitudinal direction along a first direction. In the adjacent SRAM cell units in the first direction, all the corresponding transistors have the semiconductor layer of one transistor on a center line which is along the first direction of the semiconductor layer of the other transistor.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced.

Abstract: An apparatus which manages confidentiality of information. This apparatus includes: a recording unit operable to record information in association with a history of users having accessed the information, or, with access rights defining users able to access the information; a generating unit operable to generate management information indicating whether the information should be managed confidentially from users not permitted to access the information; a selecting unit operable to select, based on the history or access rights, users able to access the information; and a notifying unit operable to notify the selected users of the generated management information in association with identification information of the information.