Abstract: A method and apparatus for associating text information with numerical information. A first phrase corresponding to a time period is generated. The first phrase represents a change in first numerical information over the time period. The first numerical information includes time-series data pertaining to a financial index. The text information is retrieved through use of a retrieval condition that includes the first phrase. The first numerical information is retrieved through use of the retrieval condition and the first phrase. The extracted text information and the retrieved first numerical information are outputted in association with each other.

Abstract: A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained.

Abstract: Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.

Abstract: A polishing apparatus includes a loading section (14) for placing therein a cassette (12) in which a plurality of polishing objects are housed; a first polishing line (20) and a second polishing line (30) for polishing a polishing object; a cleaning line (40) having cleaning machines (42a, 42b, 42c, 42d) for cleaning the polishing object after polishing and a transport unit (44) for transporting the polishing object; a transport mechanism (50) for transporting the polishing object between the loading section (14), the polishing lines (20, 30) and the cleaning line (40); and a control section for controlling the polishing lines (20, 30), the cleaning line (40) and the transport mechanism (50).

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.

Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract: A personal service support method for assisting an inquiry about a user operation in a virtual world, a computer program product, and a system for the same. The method includes: storing a dialog between a user and an agent; connecting the dialog in a list structure with another dialog in the list structure to produce a created dialog in a branch tree structure; and recording the created dialog in the branch tree structure. The computer program product tangibly embodies instructions which when implemented causes a computer to execute the steps of the method. The system includes: a dialog storage unit which stores a dialog between a user and an agent; and a dialog creating unit which connects the dialog in the list structure with another dialog in the list structure to create a dialog in a branch tree structure.

Abstract: A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased.

Abstract: The present invention provides a propofol-containing fat emulsion that can be administered with reduced vascular pain without incorporating a local anesthetic such as lidocaine; and a process for producing the same. The fat emulsion comprises 0.1 to 5 w/v % of propofol, 2 to 20 w/v % of an oily component, 0.4 to 10 w/v % of an emulsifier and 0.02 to 0.3 w/v % of at least one compound selected from the group consisting of cyclodextrins, cyclodextrin derivatives and pharmacologically acceptable salts thereof, and is in the form of a fat emulsion.

Abstract: The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption.

Abstract: A method and apparatus for associating text information with numerical information. A first phrase corresponding to a time period is generated. The first phase represents a change in first numerical information over the time period. The first numerical information includes time-series data pertaining to a financial index. The text information is retrieved through use of a retrieval condition that includes the first phrase. The first numerical information is retrieved through use of the retrieval condition and the first phrase. The extracted text information and the retrieved first numerical information are outputted in association with each other.

Abstract: The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not accessed, the hold control transistor causes the first and second inverter circuits to form the loop connected hold circuit for statically holding data. When the memory cell is accessed, the hold control transistor causes the first and second inverter circuits to be disconnected from the loop connection for dynamically holding data, thereby preventing data corruption that would otherwise possible occur due to a read operation. Moreover, a sense amplifier circuit that uses a single bit line to read data from a memory cell is disposed in a space appearing in the memory cell array, thereby effectively using the area.

Abstract: This invention provides a propofol-containing fat emulsion preparation including: 0.1 to 2 w/v % of propofol, 10 to 20 w/v % of an oily component, and 2 to 5 w/v % of an emulsifier, the weight of the oily component being in the range of about 5 to about 200 times the weight of propofol, the weight of the emulsifier being in the range of about 0.9 to about 50 times that of propofol, and the average size of emulsion particles being 180 nm or less, and a method for preparing the same. Propofol-containing fat emulsion preparation of this invention alleviates the vascular pain that occurs during the administration thereof without incorporating a local anesthetic, such as lidocaine or the like, therein.

Abstract: In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced.

Abstract: A ? gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.