Abstract: An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly.

Abstract: A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed.

Abstract: A storage structure for a microelectronic device including a chip which has completed all back-end-of-line (BEOL) processes and a solvent dissolvable polymer layer covering the surface of the chip. Since the surface of the chip is isolated from the external environment by the solvent dissolvable polymer layer, corrosion, discoloring or delamination of the chip can be avoided.

Abstract: A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two dense via openings. By doing this, via-to-via bridging defects can be avoided.

Abstract: A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two dense via openings. By doing this, via-to-via bridging defects can be avoided.

Abstract: A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

Abstract: The present invention provides a method of removing electrostatic charges from a clean room with a laminar flow apparatus. The laminar flow apparatus is disposed on a ceiling of the clean room. An ion generator at a first height and a transportation system at a second height are disposed in the laminar flow. An output tip of an emitter of the ion generator faces toward the ceiling to enlarge a divergent angle between positive and negative ions, effectively removing the electrostatic charges from the clean room and from a carrier in the transportation system.

Abstract: A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

Abstract: A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

Abstract: A lithography process. A substrate is provided first. Then a protective layer is formed on the substrate and a patterned photoresist layer is formed on a surface of the protective layer. A normal lithography process is executed. Finally a first inspection process is performed to screen the correctness of the patterned photoresist layer. When the correctness of the patterned photoresist layer does not fulfill the spec, the patterned photoresist layer on the surface of the protective layer is thereafter removed and the patterned photoresist layer is reformed on the surface of the protective layer.

Abstract: The present invention provides a method of removing electrostatic charges from a clean room with a laminar flow apparatus. The laminar flow apparatus is disposed on a ceiling of the clean room. An ion generator at a first height and a transportation system at a second height are disposed in the laminar flow. An output tip of an emitter of the ion generator faces toward the ceiling to enlarge a divergent angle between positive and negative ions, effectively removing the electrostatic charges from the clean room and from a carrier in the transportation system.

Abstract: A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

Abstract: Provided is a one time programmable read only memory, which includes a floating gate, an inter-metal dielectric layer and a control gate stacked on each other on a substrate. Furthermore, ion-implanted regions are formed in the substrate on both sides of the stacked gate structure, and are covered by metal silicide layers. The inter-metal dielectric layer comprises an oxide layer and a silicon nitride layer, wherein the oxide layer covers the floating gate, and the silicon nitride layer further covers the floating gate and the metal silicide layer. The control gate covers the silicon nitride layer. Furthermore, the one time programmable read only memory of the invention not only can reduce the electrical resistance of bit lines and enhance its own performance, but also has a small size and a greater planarity due to an absence of field oxide layers and contact windows formed thereon and therein.

Abstract: A method of transforming the OTP ROM manufacturing process into the ROM manufacturing process comprises a check step for checking the OTP ROM manufacturing process to determine which manufacturing step is already performed. If the step of depositing the polysilicon layer, acting a control gate, has already been performed, a standard OTP ROM manufacturing process is then performed. Thereafter, a coding energy is performed, in which the coding energy is about 50 KeV higher than a standard coding energy. If the step of depositing the polysilicon layer, acting a control gate, has not yet been performed, then the coding energy is about a standard coding energy. Whatever step the ongoing OTP ROM manufacturing process is on, the present invention can transform the OTP ROM manufacturing process into the ROM manufacturing process to produce ROM by the direct implanting step. It isn't necessary to redesign the masks. The size of the OTP ROM is approximately the same as the ROM so that no die surface is sacrificed.

Abstract: A method for manufacturing a CMOS sensor comprises the steps of providing a substrate having a first conductive type, wherein the substrate comprises an isolation region, an active region, a gate structure on the active region and a source/drain region having a second conductive type in the substrate. A patterned photoresist is formed over the substrate. A first doped region having the second conductive type is formed across a portion of the source/drain region and extends from the surface of the substrate into the substrate. A second doped region having the first conductive type is formed to wrap the first doped region in the substrate. A third doped region having the second conductive type is formed under the second doped region. A fourth doped region having the first conductive type is formed under the third doped region. The patterned photoresist is removed.

Abstract: A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

Abstract: A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner.

Abstract: A method is described for manufacturing a high voltage mixed-mode device. The method comprises the steps of providing a substrate, wherein the substrate comprises an isolation region, a first active region and a second active region. A first oxide layer is formed on the first active region and the second active region, wherein the thickness of the first oxide layer on the second active region is thicker than that on the first active region. A first conductive layer is formed on the first oxide layer and the isolation region. A patterned second oxide layer is formed on the first conductive layer. A patterned second conductive layer is formed on the second oxide layer and the first conductive layer. The first conductive layer is patterned to form a low-voltage transistor gate on the first active region a high voltage transistor gate on the second active region and a capacitor on the isolation region.

Abstract: A method of fabricating a mixed mode semiconductor device. A semiconductor substrate having a device isolation region and a gate oxide layer formed thereon is provided. A first conductive layer is formed to cover the device isolation region and the gate oxide layer. A dielectric layer if formed over the device isolation region to cover a part of the first conductive layer. A second conductive layer is formed on the dielectric layer and the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a capacitor and a gate.

Abstract: The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relay out of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e.