Abstract: A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative high voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches.

Abstract: A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The P-type substrate is doped using first N-type ions to form a plurality of essentially parallel N-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the N-pole regions. The P-type substrate is doped and annealed, to form a plurality of N-type diffusion regions under the exposed portions of the N-pole regions. The N-pole regions are doped and annealed, to form a plurality of P-type diffusion regions in the exposed portions of the N-pole regions. A metal layer is formed which fills the contact windows. The metal layer is patterned to form a plurality of essentially parallel word lines.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: CMOS transistors are formed by a damascene process resulting in field oxide regions exhibiting essentially no bird's beak portions. A trench isolation is also formed in a source/drain region each transistor between adjacent junctions.

Abstract: A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon nitride layer is over the N well. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The N well is doped using first P-type ions to form a plurality of essentially parallel P-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the P-pole regions. The N well is doped and annealed, to form a plurality of P-type diffusion regions under the exposed portions of the P-pole regions. The P-pole regions are doped and annealed, to form a plurality of N-type diffusion regions in the exposed portions of the P-pole regions. A metal layer is formed which fills the contact windows.

Abstract: The method includes forming a first insulating layer over a substrate. A first metal layer is formed over the first insulating layer. The first metal layer is patterned to form a plurality of parallel bit lines. A second insulating layer is formed over the bit lines and first insulating layer. At least one via is formed in the second insulating layer. Tungsten fills the via to form a tungsten plug. A second metal layer is formed over the second insulating layer. The second metal layer is patterned to form a plurality of parallel word lines. The word lines and the bit lines crosses at an angle. The present invention is also directed toward a high density ROM device that comprises a substrate and at least one memory array, including a first insulating layer located over a surface of the substrate, and a bit line located on a surface of the first insulating layer.

Abstract: A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

Abstract: The read only memory includes a number of word lines and a number of bit lines. The word lines and the bit lines are arranged in a matrix. Between every two of the bit lines and on every word line there forms a memory cell. The two bit lines of the memory cell are a first bit line and a second bit line. The method of programming includes the following steps. The first bit line is supplied with a first voltage. The second bit line is supplied with a second voltage. The word line is supplied with a third voltage. Bit lines at the same side of the first bit line are supplied with the first voltage. Bit lines at the same side of the second bit line are supplied with the second voltage.

Abstract: A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.

Abstract: A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO.

Abstract: The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relayout of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e.

Abstract: The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

Abstract: A method of fabricating a novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories is disclosed herein. Since the degree of ion implantation in the substrate determines the thichness of the silicon dioxide. The proper thickness of the silicon dioxide can be determined by considering the particular dopant to be used and degree of ion implantation, a 50-100 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E14-1E15 atoms/cm.sup.2, 100 KeV, ion implantation. A 150-350 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E11-1E13 atoms/cm.sup.2, 100 KeV, ion implantation.

Abstract: A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative low voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: A conductive via structure establishes an electrical interconnection between two conductive layers in a semiconductor structure by connecting a first conductive layer on a semiconductor substrate to a second conductive layer by means of a conductive via structure extending through a non-conductive layer separating the two conductive layers. The non-conductive layer preferably includes a layer of spin-on-glass (SOG), and is provided with a via aperture therethrough. A conductive spacer, preferably of TiW, is fabricated within the via aperture in abutment with the walls of the via aperture. A second conductive layer is fabricated over the non-conductive layer, the conductive spacer, and within the via aperture, to establish the completed electrical interconnection. The via structure reduces out-gassing and chipping from the SOG layer, yet provides a low electrical resistance path between the two conductive layers.

Abstract: A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.

Abstract: An improved process is provided for forming field dielectric in lieu of local oxidation process often referred to as the "LOCOS" process. The improved process utilizes blanket formation of first and second dielectrics across an entire semiconductor substrate. In a subsequent step, both first and second dielectrics are selectively removed in areas overlying active regions. The first and second dielectrics are formed using a combination of thermal growth and/or chemical deposition. The resulting field dielectric structure is relatively thin, yet demonstrates superior dielectric properties. Blanket formation followed by select removal ensures a fine-line demarcation between field and active regions and substantially eliminates encroachment problems normally associated with conventional LOCOS. Additionally, the thin field dielectric structure can be formed with rounded or reflowed corners to avoid step coverage problems for subsequently placed conductive elements.